Memory devices with backside bond pads under a memory array
An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.
1. An apparatus, comprising:
a substrate with a frontside and a backside opposite the frontside;
control circuitry disposed over the frontside of the substrate;
a memory array disposed over and electrically coupled to the control circuitry;
a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and
a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV,
wherein there are no bond pads on a top side of the apparatus.
2. The apparatus of claim 1 , wherein the memory array comprises a negative-and (NAND) memory array.
3. The apparatus of claim 1 , wherein the control circuitry comprises complementary metal-oxide-semiconductor (CMOS) circuitry.
4. The apparatus of claim 3 , wherein the memory array is disposed over the CMOS control circuitry in a CMOS Under Array (CUA) configuration.
5. The apparatus of claim 1 , wherein the memory array extends within a threshold distance of each edge of the substrate, the threshold distance being less than a width of the bond pad.
6. A method for manufacturing a memory die, the method comprising:
forming a through-silicon via (TSV) in a substrate that has a frontside and a backside opposite the frontside;
forming control circuitry on the frontside of the substrate;
forming a memory array over the control circuitry, wherein the memory array is electrically coupled to the control circuitry;
forming a bond pad on the backside of the substrate, wherein the bond pad is electrically coupled to the control circuitry via the TSV, and
prior to forming the bond pad, attaching a carrier wafer to a top side of the memory die opposite the backside of the substrate.
7. The method of claim 6 , further comprising singulating the memory die from a wafer.
8. The method of claim 6 , further comprising removing the carrier wafer from the memory die, following forming the bond pad.
9. The method of claim 6 , further comprising exposing the TSV by planarizing the backside of the substrate.
10. The method of claim 6 , wherein the memory array comprises NAND memory cells.
11. The method of claim 6 , wherein the control circuitry is complementary metal-oxide-semiconductor (CMOS) circuitry.
12. An apparatus, comprising:
a bond pad formed on a backside of a substrate, wherein the substrate has a frontside opposite the backside;
complementary metal-oxide-semiconductor (CMOS) circuitry disposed over the frontside of the substrate and under a memory array;
wherein the bond pad is electrically coupled to the CMOS circuitry through a via that passes through the substrate to the CMOS circuitry but does not pass through a plane containing the memory array,
wherein there are no bond pads on a top side of the apparatus.
13. The apparatus of claim 12 , wherein the via is a through-silicon via (TSV).
14. The apparatus of claim 12 , wherein the via is vertically aligned with memory array and does not penetrate the memory array.
15. The apparatus of claim 12 ,
wherein the memory array extends within a threshold distance of each edge of the substrate such that the threshold distance is smaller than a width of the bond pad; and
wherein the bond pad is vertically aligned with the memory array.
16. The apparatus of claim 12 , wherein the memory array comprises a NAND memory array.
17. The apparatus of claim 12 , wherein the via does not extend away from the bond pad past the CMOS.