Detection and mitigation of unstable cells in unclonable cell array
A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.
1. A circuit comprising:
a plurality of bit generating cells;
one or more adjustable current sources coupled to introduce changes into outputs of at least some of the bit generating cells; and
logic to select, based on the changes, less than all of the outputs to form a control value in a digital system.
2. The circuit of claim 1 , wherein the bit generating cells form an unclonable cell array.
3. The circuit of claim 2 , wherein the control value is an encryption key.
4. The circuit of claim 1 , wherein the changes are introduced with current mirrors to one or both of NFET units and PFET units of the bit generating cells.
5. The circuit of claim 4 , wherein the changes are introduced to only the NFET units.
6. The circuit of claim 4 , wherein the changes are introduced to only the PFET units.
7. The circuit of claim 4 , wherein at least some of the current mirrors are adjustable current mirrors.
8. The circuit of claim 7 , wherein at least some of the current mirrors are fixed current mirrors.
9. The circuit of claim 1 , wherein the changes are introduced by input signal delay changes to the bit generating cells.
10. The circuit of claim 1 , wherein the changes are introduced by variations to a transition voltage trigger value of the bit generating cells.
11. An encryption key generating circuit comprising:
an unclonable cell array;
logic to vary input currents to at least some cells of the unclonable cell array; and
logic to select a subset of less than all of the cells to generate the encryption key based on changes to outputs of the cells resulting from varying the input currents.
12. The encryption key generating circuit of claim 11 wherein the logic to vary the input currents comprises one or more adjustable current mirror.
13. The encryption key generating circuit of claim 12 , wherein the logic to vary the input currents comprises an adjustable PFET current mirror and an adjustable NFET current mirror.
14. The encryption key generating circuit of claim 11 wherein the logic to vary the input currents comprises one or more adjustable delay element.
15. The encryption key generating circuit of claim 11 , configured to vary the input currents of at least some cells of the unclonable cell array independently of one another.
16. The encryption key generating circuit of claim 11 , configured to share the logic to vary the input currents among a plurality of cells of the unclonable cell array.
17. A method comprising:
operating a plurality of current sources to introduce changes to outputs of a plurality of bit generating cells; and
selecting a subset less than all of the bit generating cells as a key value based on a range of the changes to the outputs.
18. The method of claim 17 , further comprising applying the key value as a master key to authenticate a software application.
19. The method of claim 17 , further comprising applying the key value to perform encryption.
20. The method of claim 17 , wherein the bit generating cells form an unclonable cell array.