Phase locked loop with parallel phase detection circuits
In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.
1. A method of operating a phase locked loop (PLL), the method comprising:
comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, wherein each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic;
filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and
controlling a frequency of an oscillator using the filtered phase detection signal, wherein the oscillator is configured to provide the clock signal.
2. The method of claim 1 , wherein:
each of the plurality of parallel matched phase detection circuits comprises a phase-frequency detector (PFD) and a charge pump coupled to an output the PFD; and
filtering the sum of the plurality of phase detection signals comprises using an analog loop filter.
3. The method of claim 1 , wherein:
each of the parallel matched phase detection circuits comprises a time-to-digital converter; and
filtering the sum of the plurality of phase detection signals comprises using a digital loop filter.
4. The method of claim 1 , further comprising:
dividing the frequency of the oscillator to form a divided clock signal, wherein dividing the frequency of the oscillator comprises using a divider coupled to an output of the oscillator.
5. The method of claim 4 , further comprising:
applying a fractional division value to an input of a quantizer; and
controlling a division ratio of the divider with an output of the quantizer.
6. The method of claim 5 , further comprising;
determining a quantization error of the quantizer; and
delaying the reference signal or the divided clock signal by a delay time based on the determined quantization error prior to comparing the phase.
7. The method of claim 6 , wherein delaying the reference signal or the divided clock signal comprises using a plurality of parallel digital-to-time converters coupled to corresponding inputs of the plurality of parallel matched phase detection circuits.
8. A phase locked loop (PLL) comprising:
a plurality of parallel matched phase detection circuits, each of the plurality of parallel matched phase detection circuits comprising a first input coupled to a reference signal node, a second input coupled to a clock signal node, and an output configured to provide a respective phase detection signal, wherein each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic;
a loop filter coupled to outputs of the plurality of parallel matched phase detection circuits; and
an oscillator having a frequency control input coupled to an output of the loop filter, wherein the oscillator is configured to provide a clock signal.
9. The PLL of claim 8 , wherein:
each of the plurality of parallel matched phase detection circuits comprises a phase-frequency detector (PFD) and a charge pump coupled to an output the PFD; and
the loop filter comprises an analog filter.
10. The PLL of claim 8 , wherein;
each of the parallel matched phase detection circuits comprises a time-to-digital converter; and
the loop filter comprises a digital filter.
11. The PLL of claim 10 , wherein the time-to-digital converter is configured to provide a multi-bit output.
12. The PLL of claim 8 , further comprising a clock divider configured to receive the clock signal and to provide a divided clock signal to the clock signal node.
13. The PLL of claim 12 , further comprising a quantizer coupled between a fractional division input and a modulo control input of the clock divider.
14. The PLL of claim 13 , further comprising:
a quantization error determination circuit coupled to the quantizer, the quantization error determination circuit configured to provide a determined quantization error value of the quantizer; and
a digital-to-time converter coupled between the reference signal node and the first input of each of the plurality of parallel matched phase detection circuits, or coupled between an output of the clock divider and the second input each phase of the plurality of parallel matched phase detection circuits, the digital-to-time converter configured to provide a first delay to a reference signal at the reference signal node or to the divided clock signal at the output of the clock divider based on the determined quantization error value.
15. The PLL of claim 14 , wherein the digital-to-time converter comprises a plurality of parallel digital-to-time converters coupled to corresponding first inputs or second inputs of the plurality of parallel matched phase detection circuits.
16. The PLL of claim 15 , further comprising a calibration circuit configured to independently calibrate a relationship between the first delay and the determined quantization error value for each of the plurality of parallel digital-to-time converters.
17. A phase locked loop (PLL) comprising:
a plurality of phase detection signal paths coupled in parallel, each phase detection signal path comprising a digital-to-time converter and a time-to-digital converter having an input coupled to an output of the digital-to-time converter, wherein each of the plurality of phase detection signal paths are configured to apply a same phase detection characteristic to a phase difference between a reference signal and a divided clock signal;
a summing circuit coupled to outputs of each of the plurality of phase detection signal paths;
a digital loop filter coupled to an output of the summing circuit;
a digitally controlled oscillator (DCO) coupled to an output of the digital loop filter;
a divider coupled between an output of the DCO and the plurality of phase detection signal paths, the divider configured to provide the divided clock signal;
a delta-sigma modulator having an output coupled to modulo control input of the divider; and
a subtraction circuit having input coupled to an input of the delta-sigma modulator and the output of the delta-sigma modulator and an output coupled to a delay control input of each digital-to-time converter of the plurality of phase detection signal paths.
18. The PLL of claim 17 , further comprising a calibration circuit configured to independently calibrate a relationship between values provided to the delay control input of each digital-to-time converter and a delay provided by each digital-time converter of the plurality of phase detection signal paths.
19. The PLL of claim 17 , wherein the digital-to-time converter of each of the plurality of phase detection signal paths comprises an input configured to receive the reference signal.
20. The PLL of claim 17 , wherein the digital-to-time converter of each of the plurality of phase detection signal paths comprises an input configured to receive the divided clock signal.