Memory device and method of forming the same
Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
1. A memory device, comprising:
a plurality of word-line structures, disposed on a substrate;
a plurality of cap structures, respectively disposed on the plurality of word-line structures, wherein each cap structure at least comprises:
a first silicon nitride layer, conformally covering and directly contacting a top surface and an upper sidewall of a corresponding word-line structure, and exposing a lower sidewall of the corresponding word-line structure;
a second silicon nitride layer, conformally covering the first silicon nitride layer; and
a third silicon nitride layer, conformally covering the second silicon nitride layer, wherein the first silicon nitride layer has a nitrogen concentration higher than a nitrogen concentration of the second silicon nitride layer, and the nitrogen concentration of the second silicon nitride layer is higher than a nitrogen concentration of the third silicon nitride layer; and
a plurality of air gaps, respectively disposed between the plurality of word-line structures, wherein the plurality of air gaps are in direct contact with the lower sidewall of the plurality of word-line structures.
2. The memory device according to claim 1 , wherein each word-line structure comprises:
a tunneling dielectric layer;
a floating gate, disposed on the tunneling dielectric layer;
a control gate, disposed on the floating gate;
an inter-gate dielectric layer, disposed between the floating gate and the control gate;
a metal layer disposed on the control gate; and
a hard mask layer, disposed on the metal layer.
3. The memory device according to claim 2 , wherein one of the plurality of cap structures covers a top surface and a sidewall of the hard mask layer.
4. The memory device according to claim 2 , further comprising a dielectric layer disposed on the plurality of cap structures and extending between two adjacent cap structures.
5. The memory device according to claim 1 , wherein each cap structure further comprises a multi-layered structure, and the multi-layered structure comprises more than three silicon nitride layers.
6. The memory device according to claim 1 , wherein two adjacent cap structures are connected to each other.
7. A memory device, comprising:
a plurality of word-line structures, disposed on a substrate;
a plurality of cap structures, respectively disposed on the plurality of word-line structures, wherein each cap structure at least comprises:
a first silicon nitride layer, conformally covering and directly contacting a top surface and an upper sidewall of a corresponding word-line structure, and exposing a lower sidewall of the corresponding word-line structure; and
a second silicon nitride layer conformally covering the first silicon nitride layer, wherein the first silicon nitride layer has a nitrogen concentration higher than a nitrogen concentration of the second silicon nitride layer; and
a dielectric layer, conformally covering the second silicon nitride layer and extending to cover the lower sidewall of the plurality of word-line structures, wherein the dielectric layer between the plurality of word-line structures is connected to each other at the upper sidewall of the plurality of word-line structures, so as to form a plurality of air gaps in the dielectric layer between the plurality of word-line structures.
8. The memory device according to claim 7 , wherein each word-line structure comprises:
a tunneling dielectric layer;
a floating gate, disposed on the tunneling dielectric layer;
a control gate, disposed on the floating gate;
an inter-gate dielectric layer, disposed between the floating gate and the control gate;
a metal layer disposed on the control gate; and
a hard mask layer, disposed on the metal layer.
9. The memory device according to claim 7 , wherein each cap structure comprises a multi-layered silicon nitride layer structure.
10. The memory device according to claim 7 , wherein the dielectric layer is in direct contact with a surface of the second silicon nitride layer and the lower sidewall of the plurality of word-line structures.