Retimer training during link speed negotiation and link training
Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.
1. A retimer module comprising:
an analog to digital converter that uses a sampling clock to digitize a receive signal;
an equalizer that converts the digitized receive signal into an equalized signal;
a decision element that derives a receive symbol stream from the equalized signal;
a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed; and
an adaptation module that disables updating of equalizer coefficients when the baud rate of the receive signal is not within said range.
2. The retimer module of claim 1 , wherein during a link speed negotiation phase, the adaptation module enables updating of the equalizer coefficients only within a predetermined window after transmission word synchronization is achieved.
3. The retimer module of claim 2 , wherein the adaptation module at least temporarily disables updating of the equalizer coefficients when detecting or initiating an ingress speed change.
4. A retimer module comprising:
an analog to digital converter that uses a sampling clock to digitize a receive signal;
an equalizer that converts the digitized receive signal into an equalized signal;
a decision element that derives a receive symbol stream from the equalized signal; and
a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed, wherein the clock recovery module includes:
a timing error unit that determines a timing error signal based at least in part on the equalization error;
a phase interpolator that obtains the sampling clock from a clock signal and a control signal derived from the timing error signal;
a phase lock loop that generates the clock signal; and
a feedback path that controls a frequency of the clock signal based at least in part on the timing error signal when the baud rate of the receive signal is within said range, wherein the feedback path includes an error accumulator that is frozen when the baud rate of the receive signal is not within said range.
5. A retimer module comprising:
an analog to digital converter that uses a sampling clock to digitize a receive signal;
an equalizer that converts the digitized receive signal into an equalized signal;
a decision element that derives a receive symbol stream from the equalized signal, wherein the decision element employs multiple decision thresholds;
a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed; and
an adaptation module that tunes the decision thresholds during four-level pulse amplitude modulation (PAM4) signaling and disables tuning during non-return to zero (NRZ) signaling.
6. The retimer module of claim 5 , wherein the adaptation module preserves the tuned decision thresholds during the NRZ signaling.
7. The retimer module of claim 5 , wherein the sets inactive decision thresholds to default values during the NRZ signaling.
8. The retimer module of claim 5 , wherein the adaptation module disables updating of equalizer coefficients when the baud rate of the receive signal is not within said range.
9. The retimer module of claim 8 , wherein during a link speed negotiation phase, the adaptation module enables updating of the equalizer coefficients only within a predetermined window after transmission word synchronization is achieved.
10. The retimer module of claim 9 , wherein the adaptation module at least temporarily disables updating of the equalizer coefficients when detecting or initiating an ingress speed change.
11. A retiming method comprising:
digitizing a receive signal in accordance with a sampling clock;
converting the digitized receive signal into an equalized signal;
obtaining a receive symbol stream from the equalized signal;
deriving the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed; and
disabling updates of equalizer coefficients when the baud rate of the receive signal is not within said range.
12. The retiming method of claim 11 , wherein during a link speed negotiation phase, updates of the equalizer coefficients are enabled only within a predetermined window after transmission word synchronization is achieved.
13. The retiming method of claim 12 , further comprising at least temporarily disabling updates of the equalizer coefficients when detecting or initiating an ingress speed change.
14. A retiming method comprising:
digitizing a receive signal in accordance with a sampling clock;
converting the digitized receive signal into an equalized signal;
obtaining a receive symbol stream from the equalized signal; and
deriving the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed, wherein said deriving the sampling clock includes:
determining a timing error signal based at least in part on the equalization error;
obtaining the sampling clock from a clock signal and a control signal derived from the timing error signal;
generating the clock signal with a phase lock loop; and
controlling a frequency of the clock signal via a feedback path based at least in part on the timing error signal when the baud rate of the receive signal is within said range,
wherein the feedback path includes an error accumulator that is frozen when the baud rate of the receive signal is not within said range.
15. A retiming method comprising:
digitizing a receive signal in accordance with a sampling clock;
converting the digitized receive signal into an equalized signal;
obtaining a receive symbol stream from the equalized signal using a decision element with multiple decision thresholds; and
deriving the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed,
wherein the decision thresholds are tuned only during four-level pulse amplitude modulation (PAM4) signaling.
16. The retiming method of claim 15 , wherein the tuned decision thresholds are preserved during non-return to zero (NRZ) signaling.
17. The retiming method of claim 15 , wherein inactive ones of the multiple decision thresholds are set to default values during non-return to zero (NRZ) signaling.
18. The retiming method of claim 15 , further comprising: disabling updates of equalizer coefficients when the baud rate of the receive signal is not within said range.
19. The retiming method of claim 18 , wherein during a link speed negotiation phase, updates of the equalizer coefficients are enabled only within a predetermined window after transmission word synchronization is achieved.
20. The retiming method of claim 19 , further comprising: at least temporarily disabling updates of the equalizer coefficients when detecting or initiating an ingress speed change.