Methods and apparatus for three dimensional NAND structure fabrication
Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.
1. A system for forming a plurality of nonvolatile memory cells, comprising:
an apparatus configured to deposit on a substrate a stack of alternating layers of a first layer of metal and a second layer of metal different from the first layer of metal;
an apparatus configured to form at least one memory hole in the stack of alternating layers of the first layer of metal and the second layer of metal;
an apparatus configured to deposit in the at least one memory hole:
a layer of silicon nitride (SiN) atop a first layer of silicon oxide (SiO);
a second layer of SiO atop the layer of SiN;
a layer of poly-silicon (poly-Si) atop the second layer of SiO to form a poly-Si channel; and
a core SiO to fill the poly-Si channel;
an apparatus configured to remove the first layer of metal to form spaces between alternating layers of the second layer of metal; and
an apparatus configured to one of deposit a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.
2. The system of claim 1 wherein one of deposit the first layer of material to partially fill the spaces to leave air gaps therein or deposit the second layer of material in the spaces is performed using one of chemical vapor deposition or atomic layer deposition.
3. The system of claim 1 , wherein deposit the first layer of metal and the second layer of metal is performed using at least one of chemical vapor deposition and physical vapor deposition.
4. The system of claim 1 , wherein remove the first layer of metal is performed using one of a dry chemical etch process containing F chemistries comprising fluorine compounds including at least one of SF 6 , CF 4 , CHF 4 , CH 3 F, C 2 F 6 , C 4 F 8 , or NF3 or a wet etch process.
5. The system of claim 1 , wherein the substrate comprises a common source layer.
6. The system of claim 5 , wherein the common source layer comprises at least one of tungsten, SiN, or poly-Si.
7. The system of claim 1 , wherein deposit in the at least one memory hole further comprises deposit a layer of aluminum oxide (AlO).
8. The system of claim 7 , wherein deposit in the at least one memory hole further comprises deposit the first layer SiO atop the layer of AlO.
9. The system of claim 8 , wherein form the at least one memory hole is performed using a dry chemical etch process containing F chemistries comprising fluorine compounds including at least one of SF 6 , CF 4 , CHF 4 , CH 3 F, C 2 F 6 , C 4 F 8 , or NF 3 .
10. The system of claim 9 , further comprising:
an apparatus configured to form at least two slits through the first layer of metal, the second layer of metal, and the layer of SiN and poly-Si using F-based chemistry;
an apparatus configured to remove the layer of SiN and poly-Si from the substrate using one of a wet etch process or chemical dry etch process;
an apparatus configured to remove, from the at least one memory hole in an area that was occupied by the layer of SiN and poly-Si prior to removal thereof, the layer of AlO, the first layer of SiO atop the layer of AlO, the layer of SiN atop the first layer of SiO, and the second layer of SiO atop the layer of SiN using the chemical dry etch process; and
an apparatus configured to deposit a layer of phosphorous doped poly-Si on the substrate in place of a removed layer of AlO, a removed first layer of SiO, a removed layer of SiN, and a removed second layer of SiO to cover a portion of the poly-Si channel.
11. The system of claim 10 , further comprising an apparatus configured to remove, from the at least one memory hole in an area that was occupied by the layer of first metal prior to removal thereof, the layer of AlO, the first layer of SiO atop the layer of AlO, and the layer of SiN atop the first layer of SiO using the chemical dry etch process.
12. The system of claim 1 , wherein the first layer of metal is at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), Ti nitride (TiN), TaN, WN, MoN, ZrN, WOx, RuOx, and IrOx,
wherein the second layer of metal is one of W, Mo, Ta, Ru, Nb, Os, Zr, Ir, Re, and Ti,
wherein the first layer of material is SiO, and
wherein the second layer of material is a low k oxide.
13. The system of claim 12 , wherein the low k oxide is one of SiO or silicon dioxide having a dielectric constant that is less than or equal to 3.9.