General padding support for convolution on systolic arrays

1. A method comprising:

receiving a request to perform convolutional computations for a neural network on a hardware circuit having a matrix computation unit, the request specifying (i) the convolutional computation to be performed on a feature tensor and a filter and (ii) padding applied to the feature tensor prior to performing the convolutional computation; and

generating instructions that when executed by the hardware circuit cause the hardware circuit to perform operations comprising:

transferring feature tensor data from a main memory of the hardware circuit to a scratchpad memory of the hardware circuit;

repeatedly performing the following operations:

identifying a current subset of the feature tensor;

determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory; and

when the memory view into the scratchpad memory for the current subset is not consistent with the memory view of the current subset in the main memory:

loading the current subset of the feature tensor from the scratchpad memory into the matrix computation unit and, during the loading, conducting a general padding on the loaded subset of the feature tensor; and

computing a matrix computation between the current subset of the feature tensor and the filter using the matrix computation unit.

2. The method of claim 1 , wherein the determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory comprises:

coordinating a corner portion of the memory view in the scratchpad memory to the memory view in the main memory; and

determining if all the portions of the memory view in the scratchpad memory is in bounds of the memory view in the main memory.

3. The method of claim 2 , wherein the coordinating a corner portion of the memory view in the scratchpad memory to the memory view in the main memory is performed by a sequencer of the hardware circuit.

4. The method of claim 1 , wherein the transferring feature tensor data comprises:

identifying an access address of the main memory, a stride length of shifting the access address in the main memory, a direct memory access size, and an access address of the scratchpad memory for storing the transferred feature tensor;

repeatedly performing the following operations:

transferring a partial block of the feature tensor data from the main memory to the scratchpad memory in a consistent memory view;

striding the access address of the scratchpad memory; and

transferring a next partial block of the feature tensor data from the main memory to the scratchpad memory in a consistent memory view.

5. The method of claim 1 , wherein the general padding comprises:

replacing one or more of values loaded from the scratchpad memory with padded values; and

utilizing one or more of values that pre-stored in the scratchpad memory and adjacent to the memory view in the scratchpad memory as padded values.

6. The method of claim 1 , wherein the general padding further comprises:

identifying a type of convolution computation in a specific convolutional neural network layer;

determining convolution parameters; and

loading the feature tensor data from the scratchpad memory to the matrix computation unit.

7. The method of claim 1 , wherein the filter is loaded from the scratchpad memory or the main memory, to the matrix computation unit prior to the loading of the feature tensor data from the scratchpad memory to the matrix computation unit.

8. The method of claim 1 , wherein the general padding further comprises:

determining convolution parameters that comprise a padding number, a size of input data, a size of output data, a size of filter data, a number of the filters, and a stride of convolution operation.

9. The method of claim 1 , wherein the conducting a general padding is performed by a sequencer and a vector computation unit of the hardware circuit.

10. The method of claim 1 , wherein the computing a matrix computation using the matrix computation unit comprises a series of vector multiplication operations.

11. A system comprising one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:

receiving a request to perform convolutional computations for a neural network on a hardware circuit having a matrix computation unit, the request specifying (i) the convolutional computation to be performed on a feature tensor and a filter and (ii) padding applied to the feature tensor prior to performing the convolutional computation; and

generating instructions that when executed by the hardware circuit cause the hardware circuit to perform operations comprising:

transferring feature tensor data from a main memory of the hardware circuit to a scratchpad memory of the hardware circuit;

repeatedly performing the following operations:

identifying a current subset of the feature tensor;

determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory; and

when the memory view into the scratchpad memory for the current subset is not consistent with the memory view of the current subset:

loading the current subset of the feature tensor from the scratchpad memory into the matrix computation unit and, during the loading, conducting a general padding on the loaded subset of the feature tensor; and

computing a matrix computation between the current subset of the feature tensor and the filter using the matrix computation unit.

12. The system of claim 11 , wherein the determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory comprises:

coordinating a corner portion of the memory view in the scratchpad memory to the memory view in the main memory; and

determining if all the portions of the memory view in the scratchpad memory is in bounds of the memory view in the main memory.

13. The system of claim 12 , wherein the coordinating a corner portion of the memory view in the scratchpad memory to the memory view in the main is performed by a sequencer of the hardware circuit.

14. The system of claim 11 , wherein the transferring feature tensor data comprises:

identifying an access address of the main memory, a stride length of shifting the access address in the main memory, a direct memory access size, and an access address of the scratchpad memory for storing the transferred feature tensor;

repeatedly performing the following operations:

transferring a partial block of the feature tensor data from the main memory to the scratchpad memory in a consistent memory view; and

striding the access address of the scratchpad memory; and

transferring a next partial block of the feature tensor data from the main memory to the scratchpad memory in a consistent memory view.

15. The system of claim 11 , wherein the general padding comprises:

replacing one or more of values loaded from the scratchpad memory with padded values; and

utilizing one or more of values that pre-stored in the scratchpad memory and adjacent to the memory view in the scratchpad memory as padded values.

16. The system of claim 11 , wherein the general padding further comprises:

identifying a type of convolution computation in a specific convolutional neural network layer;

determining convolution parameters; and

loading the feature tensor data from the scratchpad memory to the matrix computation unit.

17. The system of claim 11 , wherein the filter is loaded from the scratchpad memory or the main memory, to the matrix computation unit prior to the loading of the feature tensor data from the scratchpad memory to the matrix computation unit.

18. The system of claim 11 , wherein the general padding further comprises:

determining convolution parameters that comprise a padding number, a size of input data, a size of output data, a size of filter data, a number of the filters, and a stride of convolution operation.

19. The system of claim 11 , wherein the conducting a general padding is performed by a sequencer and a vector computation unit of the hardware circuit.

20. The system of claim 11 , wherein the computing a matrix computation using the matrix computation unit comprises a series of vector multiplication operations.