Simplified operations to read memory cells coarsely programmed via interleaved two-pass data programming techniques
A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.
1. A memory sub-system, comprising:
a processing device; and
at least one memory device, the memory device having a plurality of pages of memory cells, including a first page of memory cells and second pages of memory cells;
wherein the processing device is configured to provide a first number of data pages to the memory device and identify the first page of memory cells to store the first number of data pages;
wherein responsive to the first number of data pages, the memory device is configured to:
perform a first-pass programming of threshold voltages of memory cells in the first page of memory cells to store the first number of data pages according to a mapping between values of bits of the first number and threshold levels divided into a plurality of groups;
generate at least two pages of bits identifying group identifications of the memory cells in the first page, each respective group identification having at least two bits to identify, for a respective memory cell in the first page, a group among the plurality of groups, the group being identified to contain a threshold voltage level of the respective memory cell in the first pass programming;
buffer in the second pages in single level cell (SLC) mode the at least two pages of bits identifying the group identifications of memory cells in the first page;
read, using the group identifications, a second number of data pages back from the first page, the second number of data pages being less than the first number of data pages;
compute, based on the second number of data pages and the at least two pages of bits identifying the group identifications of memory cells in the first page, the first numbers of data pages; and
perform a second-pass programming of threshold voltages of the memory cells in the first page to store the first number of data pages according to the mapping.
2. The memory sub-system of claim 1 , wherein the memory device is configured to:
apply a bitwise logic operation, to a page from the second number of data pages and a page from the at least two pages of bits identifying the group identifications of memory cells in the first page, to recover a first data page that is in the first number of data pages but not in the second number of data pages; and
apply the bitwise logic operation, to a page from the second number of data pages and the at least two pages of bits identifying the group identifications of memory cells in the first page, to recover a second data page that is in the first number of data pages but not in the second number of data pages.
3. The memory sub-system of claim 2 , wherein the bitwise logic operation is XOR or XNOR.
4. The memory sub-system of claim 3 , wherein between each pair of closest threshold levels in each respective group in the plurality of groups, there are threshold levels each in one of the plurality of groups other than the respective group.
5. The memory sub-system of claim 4 , wherein the first number is four; and the mapping is configured to program the threshold voltage of the respective memory cell to store data in quad-level cell (QLC) mode.
6. A method, comprising:
providing, by a processing device, to a memory device a first number of data pages, the memory device having a plurality of pages of memory cells, including a first page of memory cells and second pages of memory cells;
identifying, by the processing device, the first page of memory cells to store the first number of data pages; and
storing, by the memory device, the first number of data pages to the first page of memory cells by:
performing a first-pass programming of threshold voltages of memory cells in the first page of memory cells to store the first number of data pages according to a mapping between values of bits of the first number and threshold levels divided into a plurality of groups;
generating at least two pages of bits identifying group identifications of the memory cells in the first page, each respective group identification having at least two bits to identify, for a respective memory cell in the first page, a group among the plurality of groups, the group being identified to contain a threshold voltage level of the respective memory cell in the first pass programming;
buffering in the second pages in single level cell (SLC) mode the at least two pages of bits identifying the group identifications of memory cells in the first page;
reading, using the group identifications, a second number of data pages back from the first page, the second number of data pages being less than the first number of data pages;
computing, based on the second number of data pages and the at least two pages of bits identifying the group identifications of memory cells in the first page, the first numbers of data pages; and
performing a second-pass programming of threshold voltages of the memory cells in the first page to store the first number of data pages according to the mapping.
7. The method of claim 6 , further comprising:
applying a bitwise logic operation, to a page from the second number of data pages and a page from the at least two pages of bits identifying the group identifications of memory cells in the first page, to recover a first data page that is in the first number of data pages but not in the second number of data pages.
8. The method of claim 7 , further comprising:
applying the bitwise logic operation, to a page from the second number of data pages and the at least two pages of bits identifying the group identifications of memory cells in the first page, to recover a second data page that is in the first number of data pages but not in the second number of data pages.
9. The method of claim 7 , wherein the bitwise logic operation is XNOR.
10. The method of claim 7 , wherein the bitwise logic operation is XOR.
11. The method of claim 10 , wherein between each pair of closest threshold levels in each respective group in the plurality of groups, there are threshold levels each in one of the plurality of groups other than the respective group.
12. The method of claim 11 , wherein the first number is four; and the mapping is configured to program the threshold voltage of the respective memory cell to store data in quad-level cell (QLC) mode.
13. A memory device, comprising:
a plurality of pages of memory cells, including a first page of memory cells and second pages of memory cells;
a logic circuit configured to:
receive a first number of data pages identified to be stored in the first page of memory cells;
perform a first-pass programming of threshold voltages of memory cells in the first page of memory cells to store the first number of data pages according to a mapping between values of bits of the first number and threshold levels divided into a plurality of groups;
generate at least two pages of bits identifying group identifications of the memory cells in the first page, each respective group identification having at least two bits to identify, for a respective memory cell in the first page, a group among the plurality of groups, the group being identified to contain a threshold voltage level of the respective memory cell in the first pass programming;
buffer in the second pages in single level cell (SLC) mode the at least two pages of bits identifying the group identifications of memory cells in the first page;
read, using the group identifications, a second number of data pages back from the first page, the second number of data pages being less than the first number of data pages;
compute, based on the second number of data pages and the at least two pages of bits identifying the group identifications of memory cells in the first page, the first numbers of data pages; and
perform a second-pass programming of threshold voltages of the memory cells in the first page to store the first number of data pages according to the mapping.
14. The memory device of claim 13 , wherein the logic circuit is further configured to:
apply a bitwise logic operation, to a page from the second number of data pages and a page from the at least two pages of bits identifying the group identifications of memory cells in the first page, to recover a first data page that is in the first number of data pages but not in the second number of data pages.
15. The memory device of claim 14 , wherein the logic circuit is further configured to:
apply the bitwise logic operation, to a page from the second number of data pages and the at least two pages of bits identifying the group identifications of memory cells in the first page, to recover a second data page that is in the first number of data pages but not in the second number of data pages.
16. The memory device of claim 15 , wherein the bitwise logic operation is XNOR.
17. The memory device of claim 15 , wherein the bitwise logic operation is XOR.
18. The memory device of claim 17 , wherein between each pair of closest threshold levels in each respective group in the plurality of groups, there are threshold levels each in one of the plurality of groups other than the respective group.
19. The memory device of claim 18 , wherein the first number is four; and the mapping is configured to program the threshold voltage of the respective memory cell to store data in quad-level cell (QLC) mode.