IP Library Granted Patent US 11,456,399
Granted Patent B2
US 11,456,399 · App. 16/624,930 · Granted Sep 27, 2022

Light emitting diode (LED) chip and manufacturing method and light emitting method thereof

Inventors: Zhendong Wei (Xiamen, CN); Junxian Li (Xiamen, CN); Qilong Wu (Xiamen, CN); Yingce Liu (Xiamen, CN); Hongyi Zhou (Xiamen, CN)
Assignee: Xiamen Changelight Co., Ltd.
H01L33/38H01L33/0095H01L33/44H01L2933/0016H01L2933/0025
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Quick Facts
Patent No.
US 11,456,399
App. No.
16/624,930
Granted
Sep 27, 2022
Kind
B2
Abstract

A LED chip includes a substrate, an N-type semiconductor layer, an active region, a P-type semiconductor layer, a transparent electric conductive layer, and a passivation protective layer stacked with each other in sequence. The passivation protective layer has a plurality holes corresponding to different positions of the transparent electric conductive layer respectively. A P-type electrode is electrically linked with the transparent electric conductive layer through said plurality of holes, while an N-type electrode is electrically linked with said N-type semiconductor layer.

Claims (24)

1. A manufacturing method of a LED, comprising steps of:

(a) forming an N-type semiconductor layer, an active region and a P-type semiconductor layer sequentially on a substrate;

(b) forming said transparent electric conductive layer stacked on said P-type semiconductor layer and forming at least one N-type hole extended from a transparent electric conductive layer to said N-type semiconductor layer through said P-type semiconductor layer and said active region at the same time, wherein the step (b) further comprises steps of:

stacking a transparent electric conductive base layer on said P-type semiconductor layer;

stacking a first photoresist layer on said transparent electric conductive base layer; and

etching at least one predetermined position of said first photoresist layer, said transparent electric conductive base layer, and said active region to form said at least one N-type hole and said transparent electric conductive layer simultaneously;

(c) stacking a passivation protective layer having a plurality of passive-layer holes on said transparent electric conductive layer, such that said passive-layer holes of said passivation protective layer are formed corresponding to different positions of said transparent electric conductive layer respectively, wherein an N-type exposed portion, which is extended from said passivation protective layer to said N-type semiconductor layer through said transparent electric conductive layer, said P-type semiconductor layer and said active region, is formed at a position of said at least one N-type hole, while stacking said passivation protective layer on said transparent electric conductive layer, wherein the step (c) further comprises steps of:

stacking a passive base layer on said transparent electric conductive layer;

stacking a second photoresist layer on said passive base layer; and

removing said second photoresist layer and said passive base layer at a position corresponding to said at least one N-type hole, such that said passivation protective layer and said N-type exposed portion are formed simultaneously; and

(d) electrically linking an N-type electrode to said N-type semiconductor layer, and electrically linking a P-type electrode to said P-type semiconductor layer through said plurality of passive-layer holes of said passivation protective layer.

2. The method, as recited in claim 1 , wherein in step (d), a plurality of finger members, extending from one side to an opposing side of said passivation protective layer through said plurality passive-layer holes of said passivation protective layer respectively, are formed when said P-type electrode is formed on said passivation protective layer, wherein said finger members are electrically linked with different positions of said transparent electric conductive layer respectively.

3. A manufacturing method of a LED, comprising steps of:

(a) forming an N-type semiconductor layer, an active region and a P-type semiconductor layer sequentially on a substrate;

(b) forming said transparent electric conductive layer stacked on said P-type semiconductor layer and forming at least one N-type hole extended from a transparent electric conductive layer to said N-type semiconductor layer through said P-type semiconductor layer and said active region at the same time, wherein the step (b) further comprises steps of:

stacking a transparent electric conductive base layer on said P-type semiconductor layer;

stacking a first photoresist layer on said transparent electric conductive base layer; and

etching predetermined positions of said first photoresist layer, said transparent electric conductive base layer, said active region, and said N-type semiconductor layer to form said at least one N-type hole and said transparent electric conductive layer simultaneously;

(c) stacking a passivation protective layer having a plurality of passive-layer holes on said transparent electric conductive layer, such that said passive-layer holes of said passivation protective layer are formed corresponding to different positions of said transparent electric conductive layer respectively, wherein an N-type exposed portion, extending from said passivation protective layer to said N-type semiconductor layer through said transparent electric conductive layer, said P-type semiconductor layer and said active region, is formed in said at least one N-type hole, while stacking said passivation protective layer on said transparent electric conductive layer, wherein the step (c) further comprises steps of:

stacking a passive base layer on said transparent electric conductive layer;

stacking a second photoresist layer on said passive base layer; and

removing said second photoresist layer and said passive base layer at a position corresponding to said at least one N-type hole, such that said passivation protective layer and said N-type exposed portion are formed simultaneously; and

(d) electrically linking an N-type electrode to said N-type semiconductor layer, and electrically linking a P-type electrode to said P-type semiconductor layer through said plurality of passive-layer holes of said passivation protective layer.

4. The method, as recited in claim 3 , wherein in step (d), a plurality of finger members, extending from one side to an opposing side of said passivation protective layer through said plurality passive-layer holes of said passivation protective layer respectively, are formed when said P-type electrode is formed on said passivation protective layer, wherein said finger members are electrically linked with different positions of said transparent electric conductive layer respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2019
From: WEI, ZHENDONG; LI, JUNXIAN; WU, QILONG; LIU, YINGCE; ZHOU, HONGYI
To: XIAMEN CHANGELIGHT CO., LTD.
Reel/Frame 051339/0745 →
Priority Claims (2)
CN 201810478979.1 · May 18, 2018 · national
CN 201820743497.X · May 18, 2018 · national
Continuity (1)
Related Publication 20200176635A1 · Jun 4, 2020
Cited By (1)
US 1,132,891