Fine-grained access memory controller
Systems and methods are provided to perform fine-grained memory accesses using a memory controller. The memory controller can access elements stored in memory across multiple dimensions of a matrix. The memory controller can perform accesses to non-contiguous memory locations by skipping zero or more elements across any dimension of the matrix.
1. A pooling engine for a neural network processor, the pooling engine having a memory controller configured to:
receive a set of parameters from a computation controller of the neural network processor, the computation controller being physically separate from the pooling engine, the set of parameters having been decoded by the computation controller from instructions to perform a pooling operation, wherein the set of parameters includes:
a start address to access elements stored in memory;
a first count indicator corresponding to a number of elements to be accessed in a first dimension;
a second count indicator corresponding to a number of elements to be accessed in a second dimension;
a first address offset corresponding to an address increment between each of the elements to be accessed in the first dimension; and
a second address offset corresponding to an address increment between each of the elements to be accessed in the second dimension; and
access the elements by accessing a respective address for each of the elements to be accessed based on the start address, the first count indicator, the second count indicator, the first address offset, and the second address offset such that one or more elements in the memory are skipped when accessing the elements in the memory, wherein the memory controller is configured to access the elements via a memory interface and bring the elements into the pooling engine for performing pooling operations on the elements.
2. The pooling engine of claim 1 , wherein the memory controller is further configured to:
receive an element size corresponding to a size of each element to be accessed.
3. The pooling engine of claim 1 , wherein the first address offset is related to a size of each element to be accessed and a count of elements skipped between accessing each of the elements to be accessed.
4. The pooling engine of claim 1 , wherein the respective address for a first element in the number of elements to be accessed in the first dimension is the start address, and wherein the respective address for at least one remaining element in the number of elements to be accessed in the first dimension is determined by iteratively adding the first address offset to the start address.
5. The pooling engine of claim 1 , wherein the elements to be accessed correspond to a matrix having the first dimension and the second dimension, and wherein the first count indicator corresponds to a number of columns to be accessed in the matrix.
6. The pooling engine of claim 5 , wherein the second count indicator corresponds to a number of rows to be accessed in the matrix.
7. The pooling engine of claim 6 , wherein the respective address for a first element in the number of elements to be accessed in the first dimension for a first row is the start address, and wherein the respective address for each remaining element in the number of elements to be accessed for the first row is determined by iteratively adding the first address offset to the start address.
8. The pooling engine of claim 6 further configured to:
increment a first counter value for each of the elements to be accessed in the first dimension based on the first count indicator,
wherein the respective address is determined by summing the start address with a respective first multiplication result of a multiplication between the first address offset and a respective first counter value for each of the elements to be accessed in the first dimension.
9. The pooling engine of claim 8 further configured to:
increment a second counter value for each of the rows to be accessed in the second dimension based on the second count indicator,
wherein, for each of the rows of the second count indicator, the respective address for each of the elements to be accessed is determined by summing the respective first multiplication result with a respective second multiplication result of the multiplication between the second address offset and a respective second counter value.
10. The pooling engine of claim 1 , wherein the elements stored in the memory correspond to a matrix and the number of elements to be accessed in the first dimension and the number of elements to be accessed in the second dimension corresponds to a tile of the matrix.
11. The pooling engine of claim 1 , wherein at least a portion of the one or more elements are skipped in the first dimension.
12. The pooling engine of claim 1 , wherein at least a portion of the one or more elements are skipped in the second dimension.
13. The pooling engine of claim 1 , wherein the memory controller is a circuit.
14. A method comprising:
receiving, by a memory controller of a pooling engine for a neural network processor, a set of parameters from a computation controller of the neural network processor, the computation controller being physically separate from the pooling engine, the set of parameters having been decoded by the computation controller from instructions to perform a pooling operation, wherein the set of parameters includes:
a start address to access elements stored in memory;
a first count indicator corresponding to a number of elements to be accessed in a first dimension;
a second count indicator corresponding to a number of elements to be accessed in a second dimension;
a first address offset corresponding to an address increment between each of the elements to be accessed in the first dimension; and
a second address offset corresponding to an address increment between each of the elements to be accessed in the second dimension; and
accessing, by the memory controller, the elements by accessing a respective address for each of the elements to be accessed based on the start address, the first count indicator, the second count indicator, the first address offset, and the second address offset such that one or more elements in the memory are skipped when accessing the elements in the memory, wherein the memory controller is configured to access the elements via a memory interface and bring the elements into the pooling engine for performing pooling operations on the elements.
15. The method of claim 14 , further comprising:
receiving an element size corresponding to a size of each element to be accessed.
16. The method of claim 14 , wherein accessing the elements includes reading the elements from the memory using respective addresses.