Memory cell with top electrode via

1. An integrated chip, comprising:

a memory device surrounded by a dielectric structure disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode;

a top electrode via coupling the top electrode to an upper interconnect wire;

wherein a first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via; and

wherein the first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane, the second angle less than the first angle.

2. The integrated chip of claim 1 , wherein the second outermost sidewall is a curved sidewall.

3. The integrated chip of claim 1 ,

wherein the top electrode via has a bottom surface; and

wherein the top electrode via laterally extends a first distance past a first edge of the bottom surface and a second distance past an opposing second edge of the bottom surface, the first distance being larger than the second distance.

4. The integrated chip of claim 1 , wherein the top electrode via has a bottom surface that is centered along a vertical line, the vertical line offset from a center of the top electrode via by a non-zero distance.

5. The integrated chip of claim 1 ,

wherein a bottom surface of the top electrode via extends for a first distance in a first direction and for a second distance in a second direction, the second distance larger than the first distance; and

wherein the first direction and the second direction are parallel to the upper surface of the substrate.

6. The integrated chip of claim 1 , wherein a top of the top electrode via is off centered from a bottom of the top electrode via.

7. The integrated chip of claim 1 , wherein the top electrode via has a first width extending from the first outermost sidewall to the second outermost sidewall, the first width being less than or equal to approximately 25 nm.

8. The integrated chip of claim 1 , further comprising:

a second via disposed within the dielectric structure and laterally separated from the top electrode via, wherein the top electrode via has a first width and the second via has a second width that is larger than the first width.

9. The integrated chip of claim 8 , wherein the top electrode via has a first height and the second via has a second height that is larger than the first height.

10. An integrated chip, comprising:

a memory device laterally surrounded by an inter-level dielectric (ILD) layer disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode; and

a top electrode via coupling the top electrode to an upper interconnect wire, wherein a bottom surface of the top electrode via has an oval shape.

11. The integrated chip of claim 10 , further comprising:

a second via laterally separated from the top electrode via by the ILD layer, wherein the top electrode via has a first width and the second via has a second width that is larger than the first width.

12. The integrated chip of claim 10 , further comprising:

a second via laterally separated from the top electrode via by the ILD layer, wherein the second via has a different shape than the top electrode via as viewed along a top-view.

13. The integrated chip of claim 10 , wherein the top electrode via extends below a top of the top electrode.

14. The integrated chip of claim 10 , wherein a top of the top electrode via is at least twice as wide as a bottom of the top electrode via.

15. An integrated chip, comprising:

a memory device laterally surrounded by an inter-level dielectric (ILD) material disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode; and

a top electrode via coupling the top electrode to an upper interconnect wire, wherein the top electrode via is asymmetric with respect to a line bisecting the top electrode via as viewed along a cross-sectional view of the top electrode via.

16. The integrated chip of claim 15 ,

wherein the top electrode via has a bottom surface; and

wherein the top electrode via laterally extends past the bottom surface in a first direction for a first distance and the top electrode via laterally extends past the bottom surface in an opposing second direction for a second distance that is larger than the first distance.

17. The integrated chip of claim 15 , wherein a side of the top electrode via is defined by a slope that decreases as a distance from the top electrode increases.

18. The integrated chip of claim 15 , wherein a first side of the top electrode via has a first slope and an opposing second side of the top electrode via has a second slope that is greater than the first slope.

19. The integrated chip of claim 15 , wherein a bottom of the top electrode via is off centered from a top of the top electrode via.

20. The integrated chip of claim 15 , further comprising:

a second via laterally separated from the top electrode via by the ILD material, wherein a bottom surface of the second via has a larger width than a bottom surface of the top electrode via.