Deflate compression using sub-literals for reduced complexity Huffman coding

1. A system, comprising:

a literal encoder interface, wherein:

the literal encoder interface receives a literal element that has a plurality of bits; and

the literal encoder interface divides the plurality of bits in the literal element into a first sub-literal comprising a first set of bits and a second sub-literal comprising a second set of bits;

a first Huffman code tree encoder, wherein the first Huffman code tree encoder encodes the first sub-literal using a first Huffman code tree to obtain a first sub-literal codeword;

a second Huffman code tree encoder, wherein the second Huffman code tree encoder encodes the second sub-literal using a second Huffman code tree to obtain a second sub-literal codeword; and

a multiplexer, wherein the multiplexer outputs encoded data that includes information associated with the first Huffman code tree, information associated with the second Huffman code tree, the first sub-literal codeword, and the second sub-literal codeword.

2. The system recited in claim 1 , wherein the system is implemented using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The system recited in claim 1 further including storage having a data size that is a multiple of 4,096 bytes, wherein:

the encoded data is output to the storage and is stored on the storage; and

the first Huffman code tree is further associated with a set of supported lengths having 22 supported lengths.

4. The system recited in claim 1 further including storage having a data size that is a multiple of 4,096 bytes, wherein:

the encoded data is output to the storage and is stored on the storage; and

the first Huffman code tree is further associated with a set of supported lengths having a maximum supported length of 24.

5. The system recited in claim 1 further including storage having a data size that is a multiple of 4,096 bytes, wherein:

the encoded data is output to the storage and is stored on the storage;

the first set of bits in the first sub-literal has three bits; and

the second set of bits in the second sub-literal has five bits.

6. A method, comprising:

receiving a literal element that has a plurality of bits;

dividing the plurality of bits in the literal element into a first sub-literal comprising a first set of bits and a second sub-literal comprising a second set of bits;

encoding the first sub-literal using a first Huffman code tree to obtain a first sub-literal codeword;

encoding the second sub-literal using a second Huffman code tree to obtain a second sub-literal codeword; and

outputting encoded data that includes information associated with the first Huffman code tree, information associated with the second Huffman code tree, the first sub-literal codeword, and the second sub-literal codeword.

7. The method recited in claim 6 , wherein the method is performed using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

8. The method recited in claim 6 , wherein:

the encoded data is output to a storage and is stored on the storage, wherein the storage has a data size that is a multiple of 4,096 bytes; and

the first Huffman code tree is further associated with a set of supported lengths having 22 supported lengths.

9. The method recited in claim 6 , wherein:

the encoded data is output to a storage and is stored on the storage, wherein the storage has a data size that is a multiple of 4,096 bytes; and

the first Huffman code tree is further associated with a set of supported lengths having a maximum supported length of 24.

10. The method recited in claim 6 , wherein:

the encoded data is output to a storage and is stored on the storage, wherein the storage has a data size that is a multiple of 4,096 bytes;

the first set of bits in the first sub-literal has three bits; and

the second set of bits in the second sub-literal has five bits.

11. A system, comprising:

an input interface, wherein the interface receives encoded data that includes information associated with a first Huffman code tree, information associated with a second Huffman code tree, a first sub-literal codeword, and a second sub-literal codeword;

a first Huffman code tree decoder, wherein the first Huffman code tree decoder decodes the first sub-literal codeword using the first Huffman code tree to obtain a first sub-literal comprising a first set of bits;

a second Huffman code tree decoder, wherein the second Huffman code tree decoder decodes the second sub-literal codeword using the second Huffman code tree to obtain a second sub-literal comprising a second set of bits;

a combiner, wherein the combiner combines the first set of bits in the first sub-literal and the second set of bits in the second sub-literal to obtain a literal element; and

an output interface, wherein the output interface outputs the literal element.

12. The system recited in claim 11 , wherein the system is implemented using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

13. The system recited in claim 11 further including storage having a data size that is a multiple of 4,096 bytes, wherein:

the encoded data is stored on the storage and is received from the storage; and

the first Huffman code tree is further associated with a set of supported lengths having 22 supported lengths.

14. The system recited in claim 11 further including storage having a data size that is a multiple of 4,096 bytes, wherein:

the encoded data is stored on the storage and is received from the storage; and

the first Huffman code tree is further associated with a set of supported lengths having a maximum supported length of 24.

15. The system recited in claim 11 further including storage having a data size that is a multiple of 4,096 bytes, wherein:

the encoded data is stored on the storage and is received from the storage;

the first set of bits in the first sub-literal has three bits; and

the second set of bits in the second sub-literal has five bits.

16. A method, comprising:

receiving encoded data that includes information associated with a first Huffman code tree, information associated with a second Huffman code tree, a first sub-literal codeword, and a second sub-literal codeword;

decoding the first sub-literal codeword using the first Huffman code tree to obtain a first sub-literal comprising a first set of bits;

decoding the second sub-literal codeword using the second Huffman code tree to obtain a second sub-literal comprising a second set of bits;

combining the first set of bits in the first sub-literal and the second set of bits in the second sub-literal to obtain a literal element; and

outputting the literal element.

17. The method recited in claim 16 , wherein the method is performed using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

18. The method recited in claim 16 , wherein:

the encoded data is stored on a storage and is received from the storage, wherein the storage has a data size that is a multiple of 4,096 bytes; and

the first Huffman code tree is further associated with a set of supported lengths having 22 supported lengths.

19. The method recited in claim 16 , wherein:

the encoded data is stored on a storage and is received from the storage, wherein the storage has a data size that is a multiple of 4,096 bytes; and

the first Huffman code tree is further associated with a set of supported lengths having a maximum supported length of 24.

20. The method recited in claim 16 , wherein:

the encoded data is stored on a storage and is received from the storage, wherein the storage has a data size that is a multiple of 4,096 bytes;

the first set of bits in the first sub-literal has three bits; and

the second set of bits in the second sub-literal has five bits.