IP Library › Granted Patent US 11,474,738
Granted Patent B1
US 11,474,738 · App. 17/232,063 · Granted Oct 18, 2022

Probabilistic data integrity scan enhanced by a supplemental data integrity scan

Inventors: Saeed Sharifi Tehrani (San Diego, CA); Ashutosh Malshe (Fremont, CA); Kishore Kumar Muchherla (Fremont, CA); Sivagnanam Parthasarathy (Carlsbad, CA); Vamsi Pavan Rayaprolu (San Jose, CA)
Assignee: MICRON TECHNOLOGY, INC.
G06F3/0655G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,474,738
App. No.
17/232,063
Granted
Oct 18, 2022
Kind
B1
Abstract

Exemplary methods, apparatuses, and systems include receiving a plurality of read operations directed to a portion of memory accessed by a memory channel. The plurality of read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A supplemental memory location is selected independently of aggressors and victims in the current set of read operations. A first data integrity scan is performed on a victim of the aggressor read operation and a second data integrity scan is performed on the supplemental memory location.

Claims (46)

1. A method comprising:

receiving, by a processing device, a plurality of read operations directed to a portion of memory accessed by a memory channel, the plurality of read operations divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations;

selecting, by the processing device, an aggressor read operation from the current set;

selecting, by the processing device, a supplemental memory location independently of aggressors and victims in the current set of read operations; and

performing, by the processing device, a first data integrity scan on a victim of the aggressor read operation and a second data integrity scan of the supplemental memory location.

2. The method of claim 1 , wherein the supplemental memory location is randomly selected.

3. The method of claim 1 , wherein the supplemental memory location is selected as a part of a deterministic rotation through memory locations.

4. The method of claim 1 , further comprising:

maintaining, by the processing device, a limited history of memory locations subject to a data integrity scan in one or more previous sets of read operations, wherein selecting the supplemental memory location includes determining that the supplemental memory location is not included in the limited history of memory locations.

5. The method of claim 1 , further comprising:

maintaining, by the processing device, a limited history of aggressor memory locations in one or more previous sets of read operations, wherein selecting the supplemental memory location includes selecting a memory location from the limited history of aggressor memory locations.

6. The method of claim 5 , further comprising:

removing, by the processing device, the selected aggressor memory location from the limited history of victim memory locations.

7. The method of claim 1 , wherein each set includes N read operations, the method further comprising:

generating, by the processing device, a first random number that is less than or equal to N, wherein selecting the aggressor read operation includes selecting a read operation that is in a position in the current set indicated by the first random number.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receive a plurality of read operations directed to a portion of memory accessed by a memory channel, the plurality of read operations divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations;

select an aggressor read operation from the current set;

select a supplemental memory location independently of aggressors and victims in the current set of read operations; and

perform a first data integrity scan on a victim of the aggressor read operation and a second data integrity scan of the supplemental memory location.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the supplemental memory location is randomly selected.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the supplemental memory location is selected as a part of a deterministic rotation through memory locations.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

maintain a limited history of memory locations subject to a data integrity scan in one or more previous sets of read operations, wherein selecting the supplemental memory location includes determining that the supplemental memory location is not included in the limited history of memory locations.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

maintain a limited history of aggressor memory locations in one or more previous sets of read operations, wherein selecting the supplemental memory location includes selecting a memory location from the limited history of aggressor memory locations.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the processing device is further to:

remove the selected aggressor memory location from the limited history of victim memory locations.

14. The non-transitory computer-readable storage medium of claim 8 , wherein each set includes N read operations, and wherein the processing device is further to:

generate a first random number that is less than or equal to N, wherein selecting the aggressor read operation includes selecting a read operation that is in a position in the current set indicated by the first random number.

15. A system comprising:

a plurality of memory devices; and

a processing device, operatively coupled with the plurality of memory devices, to:

receive a plurality of read operations directed to a portion of memory accessed by a memory channel, the plurality of read operations divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations, wherein each set includes N read operations;

generate a first random number that is less than or equal to N;

select an aggressor read operation from the current set, wherein selecting the aggressor read operation includes selecting a read operation that is in a position in the current set indicated by the first random number;

select a supplemental memory location independently of aggressors and victims in the current set of read operations; and

perform a first data integrity scan on a victim of the aggressor read operation and a second data integrity scan of the supplemental memory location.

16. The system of claim 15 , wherein the supplemental memory location is randomly selected.

17. The system of claim 15 , wherein the supplemental memory location is selected as a part of a deterministic rotation through memory locations.

18. The system of claim 15 , wherein the processing device is further to:

maintain a limited history of memory locations subject to a data integrity scan in one or more previous sets of read operations, wherein selecting the supplemental memory location includes determining that the supplemental memory location is not included in the limited history of memory locations.

19. The system of claim 15 , wherein the processing device is further to:

maintain a limited history of aggressor memory locations in one or more previous sets of read operations, wherein selecting the supplemental memory location includes selecting a memory location from the limited history of aggressor memory locations.

20. The system of claim 19 , wherein the processing device is further to:

remove the selected aggressor memory location from the limited history of victim memory locations.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2021
From: TEHRANI, SAEED SHARIFI; MALSHE, ASHUTOSH; MUCHHERLA, KISHORE KUMAR; PARTHASARATHY, SIVAGNANAM; RAYAPROLU, VAMSI PAVAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 056609/0027 →