Scalable peer to peer data routing for servers

1. A circuit comprising:

a bus request queue configured to store a data request received from a first peer device via a peer-to-peer (P2P) controller;

a decoder configured to compare an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory;

a bus interface unit configured to, in response to the data request being directed to the second peer device, 1) generate a memory access request from the bus request and 2) transmit the memory access request toward the second peer device via a bus; and

a memory controller configured to, in response to the data request being directed to a local memory, access the local memory to perform a memory access operation based on the data request.

2. The circuit of claim 1 , wherein the memory access request is a direct memory access (DMA) request.

3. The circuit of claim 1 , wherein the memory access request is a write request, and further comprising a reorder queue configured to maintain an ordered list of write requests including the write request.

4. The circuit of claim 3 , further comprising a write data buffer configured to store data associated with the write request.

5. The circuit of claim 4 , wherein the bus interface unit is further configured to transmit the data associated with the write request in a relative order as a function of the ordered list maintained by the reorder queue.

6. The circuit of claim 1 , wherein the memory access request is a read request.

7. The circuit of claim 1 , further comprising a translation unit configured to modify the memory access request, based on an address lookup table, to identify a target address at the second peer device and to handle data completions and responses received from the second peer device.

8. The circuit of claim 1 , further comprising mesh routing circuitry configured to enable peer-to-peer traffic flow between the first and second peer devices via the bus interface unit.

9. The circuit of claim 8 , wherein the mesh routing circuitry includes a plurality of ingress ports and egress ports and a lookup table, the mesh routing circuity configured to determine a path between the first and second peer devices based on the lookup table.

10. The circuit of claim 1 , further comprising a merge unit configured to merge a plurality of partial cache lines into a single data packet, the partial cache lines being a target of the memory access request.

11. The circuit of claim 1 , further comprising request validation circuitry configured to determine whether the data request is compliant with a PCIe Access Control Capabilities (ACS) structure.

12. The circuit of claim 1 , wherein the P2P controller is a peripheral component interconnect express (PCIe) controller.

13. The circuit of claim 1 , wherein the first and second peer devices are one or more of a graphics processing unit (GPU), solid state drive (SSD), and a network interface controller (NIC).

14. A method of processing peer-to-peer data traffic comprising:

storing a data request to a bus request queue, the data request being received from a first peer device via a peer-to-peer (P2P) controller;

comparing, via a decoder, an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory;

in response to the data request being directed to the second peer device, 1) generating, via a bus interface unit, a memory access request from the bus request, and 2) transmitting, via the bus interface unit, the memory access request toward the second peer device via a bus; and

in response to the data request being directed to a local memory, accessing, via a memory controller, the local memory to perform a memory access operation based on the data request.

15. The method of claim 14 , wherein the memory access request is a direct memory access (DMA) request.

16. The method of claim 14 , wherein the memory access request is a write request, and further comprising maintaining, via a reorder queue, an ordered list of write requests including the write request.

17. The method of claim 16 , further comprising storing data associated with the write request to a write data buffer.

18. The method of claim 17 , further comprising transmitting, via the bus interface unit, the data associated with the write request in a relative order as a function of the ordered list maintained by the reorder queue.

19. The method of claim 14 , wherein the memory access request is a read request.

20. The method of claim 14 , further comprising modifying, via a translation unit, the memory access request, based on an address lookup table, to identify a target address at the second peer device and to handle data completions and responses received from the second peer device.

21. A system for processing peer-to-peer data traffic comprising:

means for storing a data request, the data request being received from a first peer device via a peer-to-peer (P2P) controller;

means for comparing an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory;

means for, in response to the data request being directed to the second peer device, 1) generating a memory access request from the bus request, and 2) transmitting the memory access request toward the second peer device via a bus; and

means for, in response to the data request being directed to a local memory, accessing the local memory to perform a memory access operation based on the data request.