Spike suppression circuit and power converter and control method thereof
A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.
1. A spike suppression circuit, comprising:
a wide bandgap transistor, wherein the wide bandgap transistor is depletion-type;
a first transistor, coupled in series with the wide bandgap transistor;
a clamping circuit, providing a voltage difference, and coupled to a common node between the wide bandgap transistor and the first transistor; and
a capacitor, providing a supply voltage for the clamping circuit;
wherein when the first transistor is turned off, the capacitor is capable of recycling spike energy at the common node.
2. The spike suppression circuit as claimed in claim 1 , further comprising:
a control circuit, generating a selection voltage according to the supply voltage, such that the spike suppression circuit operates in an initial mode or a stable mode.
3. The spike suppression circuit as claimed in claim 2 , wherein the wide bandgap transistor has a control terminal coupled to a control node, a first terminal coupled to the common node, and a second terminal coupled to an external node.
4. The spike suppression circuit as claimed in claim 3 , further comprising:
a second Zener diode, wherein the second Zener diode has an anode coupled to a ground voltage, and a cathode coupled to the control node.
5. The spike suppression circuit as claimed in claim 3 , further comprising:
a second transistor, wherein the second transistor has a control terminal for receiving the selection voltage, a first terminal coupled to a ground voltage, and a second terminal coupled to the control node; and
a large resistor, wherein the large resistor has a first terminal coupled to the control node, and a second terminal coupled to the common node.
6. The spike suppression circuit as claimed in claim 2 , wherein the capacitor has a first terminal coupled to a supply node for outputting the supply voltage, and a second terminal coupled to a ground voltage.
7. The spike suppression circuit as claimed in claim 6 , further comprising:
an LDO (Low-Dropout Regulator), coupled to the supply node, wherein the LDO is configured to stabilize the supply voltage.
8. The spike suppression circuit as claimed in claim 6 , wherein the clamping circuit comprises:
a first Zener diode, wherein the first Zener diode has an anode coupled to the supply node, and a cathode coupled to an internal node; and
a first diode, wherein the first diode has an anode coupled to the common node, and a cathode coupled to the internal node.
9. The spike suppression circuit as claimed in claim 8 , further comprising:
a switch element, controlled according to the selection voltage, wherein the switch element has a first terminal coupled to the supply node, and a second terminal coupled to the internal node;
wherein the switch element is closed in the initial mode, and the switch element is opened in the stable mode.
10. The spike suppression circuit as claimed in claim 2 , wherein the control circuit has hysteresis characteristics, the selection voltage becomes a high logic level when the supply voltage rises up to an enable threshold value, and the selection voltage becomes a low logic level when the supply voltage falls down to a disable threshold value.
11. The spike suppression circuit as claimed in claim 2 , wherein the control circuit comprises:
a voltage divider, comprising a second resistor and a third resistor coupled in series, wherein the voltage divider generates a divided voltage according to the supply voltage;
a hysteresis comparator, comparing the divided voltage with a first threshold value and a second threshold value, so as to generate a comparison voltage; and
an inverter, inverting the comparison voltage, so as to generate the selection voltage.
12. The spike suppression circuit as claimed in claim 1 , wherein the supply voltage plus the voltage difference is greater than an absolute value of a threshold voltage of the wide bandgap transistor.
13. The spike suppression circuit as claimed in claim 1 , wherein the first transistor has a control terminal for receiving a PWM (Pulse Width Modulation) voltage, a first terminal coupled to a connection node, and a second terminal coupled to the common node.
14. The spike suppression circuit as claimed in claim 13 , further comprising:
a first resistor, wherein the first resistor has a first terminal coupled to the connection node, and a second terminal coupled to a ground voltage.
15. The spike suppression circuit as claimed in claim 1 , wherein the wide bandgap transistor has a control terminal coupled to a ground voltage, a first terminal coupled to the common node, and a second terminal coupled to an external node.
16. A power converter, comprising:
a transformer, generating an output voltage according to an input voltage; and
a spike suppression circuit, coupled to the transformer, and comprising:
a wide bandgap transistor, wherein the wide bandgap transistor is depletion-type;
a first transistor, coupled in series with the wide bandgap transistor;
a clamping circuit, providing a voltage difference, and coupled to a common node between the wide bandgap transistor and the first transistor; and
a capacitor, providing a supply voltage for the clamping circuit;
wherein when the first transistor is turned off, the capacitor is capable of recycling spike energy at the common node.
17. The power converter as claimed in claim 16 , wherein the power converter is a flyback converter and supports USB PD (Universal Serial Bus Power Delivery).
18. The power converter as claimed in claim 16 , wherein the transformer comprises:
a main coil, wherein the main coil has a first terminal for receiving the input voltage, and a second terminal coupled to the wide bandgap transistor;
a secondary coil, wherein the secondary coil has a first terminal coupled to an output node, and a second terminal coupled to a ground voltage; and
an auxiliary coil, wherein the auxiliary coil has a first terminal coupled to a feedback node, and a second terminal coupled to the ground voltage.
19. The power converter as claimed in claim 18 , further comprising:
an LDO (Low-Dropout Regulator), configured to stabilize the supply voltage;
a second diode, wherein the second diode has an anode coupled to the feedback node, and a cathode coupled to the LDO; and
a third diode, wherein the third diode has an anode coupled to the output node, and a cathode for outputting the output voltage.
20. A control method for spike suppression, comprising the steps of:
coupling a wide bandgap transistor in series with a first transistor, wherein the wide bandgap transistor is depletion-type;
providing a voltage difference by a clamping circuit, wherein the clamping circuit is coupled to a common node between the wide bandgap transistor and the first transistor; and
providing a supply voltage for the clamping circuit by a capacitor;
wherein when the first transistor is turned off, the capacitor is capable of recycling spike energy at the common node.