IP Library Granted Patent US 11,489,758
Granted Patent B1
US 11,489,758 · App. 17/480,198 · Granted Nov 1, 2022

Path computation for unordered inclusion and regional revisit constraints

Inventors: Ankur Jain (Gurgaon, IN); John Wade Cherrington (Salt Spring Island, CA); Suvendu Kumar Barik (Noida, IN); Sourabh Vijay (Jaipur, IN)
Assignee: Ciena Corporation
H04L45/122H04L45/02H04L45/24H04L45/586H04L45/66
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Quick Facts
Patent No.
US 11,489,758
App. No.
17/480,198
Granted
Nov 1, 2022
Kind
B1
Abstract

Systems and methods include receiving a request for a path from a source node to a destination node in a network with the request including N unordered inclusion nodes, N≥1; adding a virtual vertex in a graph with edges connected to each of the N inclusion nodes, wherein the graph includes the virtual vertex, vertices representing nodes in the network, and edges representing links; determining a shortest path from the source node to the virtual vertex and removing an edge from a first inclusion node, that is on the shortest path, from the virtual vertex; if N>1, determining a shortest path N times to find path segments between the N inclusion nodes, removing an edge from each of the N inclusion nodes from the virtual vertex when on a corresponding shortest path; and determining a shortest path from a last inclusion node to the destination node.

Claims (45)

1. A non-transitory computer-readable medium having instructions stored thereon for programming a processing device to perform steps of:

receiving a request for a path from a source node to a destination node in a network with the request including N unordered inclusion nodes, N≥1;

adding a virtual vertex in a graph with edges connected to each of the N unordered inclusion nodes, wherein the graph includes the virtual vertex, vertices representing nodes in the network, and edges representing links in the network, wherein the virtual vertex does not represent a node in the network and includes edges to it form each of the N unordered inclusion nodes for determining paths thereto;

determining a shortest path from the source node to the virtual vertex and removing an edge from a first inclusion node, that is on the shortest path, from the virtual vertex;

if N>1, determining a shortest path N times to find path segments between the N unordered inclusion nodes, removing an edge from each of the N unordered inclusion nodes from the virtual vertex when on a corresponding shortest path; and

determining a shortest path from a last unordered inclusion node to the destination node.

2. The non-transitory computer-readable medium of claim 1 , wherein the steps further include

either removing or ignoring all edges out of the N unordered inclusion nodes while there is an edge to the virtual vertex, to avoid regional revisit on a path segment.

3. The non-transitory computer-readable medium of claim 2 , wherein the network is an optical network, and the regional revisit includes avoidance of a same network element more than once.

4. The non-transitory computer-readable medium of claim 2 , wherein the network is an Ethernet network, and the regional revisit includes avoidance of a same protection or logical ring more than once.

5. The non-transitory computer-readable medium of claim 1 , wherein the determining a shortest path is k-shortest paths.

6. The non-transitory computer-readable medium of claim 1 , wherein the steps further include

concurrently performing a path computation from the destination node to the source node via path segments; and

terminating when a path is found first in either direction.

7. The non-transitory computer-readable medium of claim 1 , wherein the determining the shortest path from the source node to the virtual vertex includes forcing a first segment through each of the N unordered inclusion nodes.

8. A method comprising steps of:

receiving a request for a path from a source node to a destination node in a network with the request including N unordered inclusion nodes, N≥1;

adding a virtual vertex in a graph with edges connected to each of the N unordered inclusion nodes, wherein the graph includes the virtual vertex, vertices representing nodes in the network, and edges representing links in the network, wherein the virtual vertex does not represent a node in the network and includes edges to it from each of the N unordered inclusion nodes for determining paths thereto;

determining a shortest path from the source node to the virtual vertex and removing an edge from a first inclusion node, that is on the shortest path, from the virtual vertex;

if N>1, determining a shortest path N times to find path segments between the N unordered inclusion nodes, removing an edge from each of the N unordered inclusion nodes from the virtual vertex when on a corresponding shortest path; and

determining a shortest path from a last unordered inclusion node to the destination node.

9. The method of claim 8 , wherein the steps further include either removing or ignoring all edges out of the N unordered inclusion nodes while there is an edge to the virtual vertex, to avoid regional revisit on a path segment.

10. The method of claim 9 , wherein the network is an optical network, and the regional revisit includes avoidance of a same network element more than once.

11. The method of claim 9 , wherein the network is an Ethernet network, and the regional revisit includes avoidance of a same protection or logical ring more than once.

12. The method of claim 8 , wherein the determining a shortest path is k-shortest paths.

13. The method of claim 8 , wherein the steps further include

concurrently performing a path computation from the destination node to the source node via path segments; and

terminating when a path is found first in either direction.

14. The method of claim 8 , wherein the determining the shortest path from the source node to the virtual vertex includes forcing a first segment through each of the N unordered inclusion nodes.

15. An apparatus comprising at least one processor and memory storing instructions that, when executed, cause the at least one processor to perform steps of:

receiving a request for a path from a source node to a destination node in a network with the request including N unordered inclusion nodes, N≥1;

adding a virtual vertex in a graph with edges connected to each of the N unordered inclusion nodes, wherein the graph includes the virtual vertex, vertices representing nodes in the network, and edges representing links in the network, wherein the virtual vertex does not represent a node in the network and includes edges to it from each of the N unordered inclusion nodes for determining paths thereto;

determining a shortest path from the source node to the virtual vertex and removing an edge from a first inclusion node, that is on the shortest path, from the virtual vertex;

if N>1, determining a shortest path N times to find path segments between the N unordered inclusion nodes, removing an edge from each of the N unordered inclusion nodes from the virtual vertex when on a corresponding shortest path; and

determining a shortest path from a last unordered inclusion node to the destination node.

16. The apparatus of claim 15 , wherein the steps further include

either removing or ignoring all edges out of the N unordered inclusion nodes while there is an edge to the virtual vertex, to avoid regional revisit on a path segment.

17. The apparatus of claim 16 , wherein one of

the network is an optical network, and the regional revisit includes avoidance of a same network element more than once, and

the network is an Ethernet network, and the regional revisit includes avoidance of a same protection or logical ring more than once.

18. The apparatus of claim 15 , wherein the determining a shortest path is k-shortest paths.

19. The apparatus of claim 15 , wherein the steps further include

concurrently performing a path computation from the destination node to the source node via path segments; and

terminating when a path is found first in either direction.

20. The apparatus of claim 15 , wherein the determining the shortest path from the source node to the virtual vertex includes forcing a first segment through each of the N unordered inclusion nodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2021
From: JAIN, ANKUR; CHERRINGTON, JOHN WADE; BARIK, SUVENDU KUMAR; VIJAY, SOURABH
To: CIENA CORPORATION
Reel/Frame 057540/0077 →
Priority Claims (1)
IN 202111035915 · Aug 9, 2021 · national
Cited By (2)
US 12,513,077 US 12,584,754