Managing write disturb for units of memory in a memory sub-system using a randomized refresh period
A write operation performed on a first memory unit of a memory device is detected, wherein the first memory unit comprises one or more memory cells. Responsive to detecting the write operation, a value of a counter associated with the first memory unit is incremented. It is determined whether the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a defined range. Responsive to determining that the value of the counter satisfies the threshold criterion, a refresh operation is performed on a second memory unit.
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
detecting a write operation performed on a first memory unit of the memory device, wherein the first memory unit comprises one or more memory cells;
responsive to detecting the write operation, incrementing a value of a counter associated with the first memory unit;
determining that the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a defined range; and
responsive to determining that the value of the counter satisfies the threshold criterion, performing a refresh operation on a second memory unit.
2. The system of claim 1 , further comprising:
responsive to performing the refresh operation on the second memory unit, resetting the value of the counter to an initial value.
3. The system of claim 1 , wherein performing the refresh operation comprises:
reading data from the second memory unit;
performing an error correction operation on the data; and
writing the data back to the second memory unit.
4. The system of claim 1 , wherein the second memory unit comprises one or more memory cells adjacent to the one or more memory cells of the first memory unit.
5. The system of claim 1 , wherein the defined range comprises a set of values having an upper limit and a lower limit.
6. The system of claim 1 , wherein the value of the counter corresponds to a number of occurrences of write operations to the first memory unit.
7. The system of claim 1 , wherein the value of the counter is stored in a data structure associated with the memory device.
8. A method comprising:
detecting a write operation performed on a first memory unit of a memory device, wherein the first memory unit comprises one or more memory cells;
responsive to detecting the write operation, incrementing a value of a counter associated with the first memory unit;
determining that the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a defined range; and
responsive to determining that the value of the counter satisfies the threshold criterion, performing a refresh operation on a second memory unit.
9. The method of claim 8 , further comprising:
responsive to performing the refresh operation on the second memory unit, resetting the value of the counter to an initial value.
10. The method of claim 8 , wherein performing the refresh operation comprises:
reading data from the second memory unit;
performing an error correction operation on the data; and
writing the data back to the second memory unit.
11. The method of claim 8 , wherein the second memory unit comprises one or more memory cells adjacent to the one or more memory cells of the first memory unit.
12. The method of claim 8 , wherein the defined range comprises a set of values having an upper limit and a lower limit.
13. The method of claim 8 , wherein the value of the counter corresponds to a number of occurrences of write operations to the first memory unit.
14. The method of claim 8 , wherein the value of the counter is stored in a data structure associated with the memory device.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
defining a range of numbers with an upper limit and a lower limit;
determining a threshold criterion based on a random or pseudo-random number within the defined range;
detecting a write operation performed on a first memory unit of a memory device, wherein the first memory unit comprises one or more memory cells;
responsive to detecting the write operation, incrementing a value of a counter associated with the first memory unit;
determining that the value of the counter satisfies the threshold criterion; and
responsive to determining that the value of the counter satisfies the threshold criterion, performing a refresh operation on a second memory unit.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:
responsive to performing the refresh operation on the second memory unit, resetting the value of the counter to an initial value.
17. The non-transitory computer-readable storage medium of claim 15 , wherein performing the refresh operation comprises:
reading data from the second memory unit;
performing an error correction operation on the data; and
writing the data back to the second memory unit.
18. The non-transitory computer-readable storage medium of claim 15 , wherein the second memory unit comprises one or more memory cells adjacent to the one or more memory cells of the first memory unit.
19. The non-transitory computer-readable storage medium of claim 15 , wherein the value of the counter corresponds to a number of occurrences of write operations to the first memory unit.
20. The non-transitory computer-readable storage medium of claim 15 , wherein the value of the counter is stored in a data structure associated with the memory device.