IP Library Granted Patent US 11,508,587
Granted Patent B2
US 11,508,587 · App. 16/648,645 · Granted Nov 22, 2022

Microelectronic assemblies

Inventors: Adel A. Elsherbini (Chandler, AZ); Shawna M. Liff (Scottsdale, AZ); Johanna M. Swan (Scottsdale, AZ)
Assignee: Intel Corporation
H01L21/4857H01L21/486H01L23/5383H01L23/5384H01L29/66007H05K3/303
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Quick Facts
Patent No.
US 11,508,587
App. No.
16/648,645
Granted
Nov 22, 2022
Kind
B2
Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

Claims (16)

1. A microelectronic assembly, comprising:

a package substrate including a plurality of layers, wherein the plurality of layers include a first layer, a second layer, a third layer, and a fourth layer;

a die having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, wherein the die is embedded in the first layer of the package substrate, and wherein the first and second conductive contacts are coupled to conductive pathways in the package substrate;

a heat spreader in the second layer of the package substrate, wherein the second layer is on the first layer and the heat spreader is in contact with the second surface of the die;

a conductive plane in the third layer of the package substrate, wherein the third layer is on the second layer and the conductive plane is in contact with the heat spreader; and

a channel in the fourth layer of the package substrate, wherein the fourth layer is on the third layer, and wherein the conductive plane provides at least a portion of a wall of the channel.

2. The microelectronic assembly of claim 1 , wherein the die has a thickness between 10 um and 50 um.

3. The microelectronic assembly of claim 1 , wherein the channel is one of a plurality of channels.

4. The microelectronic assembly of claim 1 , further comprising:

a fluid in the channel.

5. The microelectronic assembly of claim 4 , wherein the fluid includes a coolant.

6. The microelectronic assembly of claim 5 , wherein the coolant includes water.

7. The microelectronic assembly of claim 4 , further comprising:

a pump for circulating the fluid through the channel.

8. The microelectronic assembly of claim 1 , wherein the die is a first die, and the microelectronic assembly further comprising:

a second die embedded in a fifth layer of the package substrate, wherein the fifth layer is below the first layer, and wherein the second die at least partially overlaps the first die.

Continuity (1)
Related Publication 20200286745A1 · Sep 10, 2020
Cited By (1)
US 12,237,246