Receiving circuit and associated signal processing method

1. A receiving circuit, comprising:

a first analog-to-digital converter (ADC), configured to perform an analog-to-digital operation on an analog input signal to generate a first digital input signal;

an attenuator, configured to reduce strength of the analog input signal to generate an attenuated analog input signal;

a second ADC, configured to perform the analog-to-digital operation on the attenuated analog input signal to generate a second digital input signal;

a harmonic generation circuit, coupled to the second ADC, configured to generate at least one harmonic signal according to the second digital input signal; and

an output circuit, coupled to the first ADC and the harmonic generation circuit, configured to delete a harmonic component of the first digital input signal by using the at least one harmonic signal to generate an output signal.

2. The receiving circuit of claim 1 , wherein the harmonic generation circuit calculates the at least one harmonic signal according to a frequency component of the second digital input signal.

3. The receiving circuit of claim 1 , wherein the output circuit directly subtracts the at least one harmonic signal from the first digital input signal to generate the output signal.

4. The receiving circuit of claim 1 , wherein the harmonic generation circuit comprises:

a harmonic calculation circuit, configured to calculate at least one initial harmonic signal according to the second digital input signal; and

a gain adjustment circuit, configured to adjust a gain of the at least one initial harmonic signal to generate the at least one harmonic signal.

5. The receiving circuit of claim 4 , wherein the harmonic generation circuit further comprises:

a phase adjustment circuit, wherein the gain adjustment circuit and the phase adjustment circuit adjust the gain and a phase of the at least one initial harmonic signal to generate the at least one harmonic signal.

6. The receiving circuit of claim 5 , further comprising:

a calibration circuit, coupled to the output circuit and the harmonic generation circuit, configured to adjust a gain setting of the gain adjustment circuit and phase adjustment amount of the phase adjustment circuit according to the output signal.

7. The receiving circuit of claim 6 , wherein the calibration circuit adjusts the gain setting of the gain adjustment circuit and the phase adjustment amount of the phase adjustment circuit according to a strength of a harmonic component of the output signal, to make the strength of the harmonic component of the output signal be lower than a threshold value.

8. The receiving circuit of claim 4 , further comprising:

a delay circuit, coupled between the first ADC and the output circuit, configured to delay a phase of the first digital input signal inputted into the output circuit.

9. The receiving circuit of claim 4 , wherein the at least one initial harmonic signal comprises a second harmonic and a third harmonic.

10. A signal processing method, comprising:

performing an analog-to-digital operation on an analog input signal to generate a first digital output signal;

reducing strength of the analog input signal to generate an attenuated analog input signal;

performing the analog-to-digital operation on the attenuated analog input signal to generate a second digital input signal;

generating at least one harmonic signal according to the second digital input signal; and

deleting a harmonic component of the first digital input signal by using the at least one harmonic signal to generate an output signal.

11. The signal processing method of claim 10 , wherein the step of generating the at least one harmonic signal according to the second digital input signal comprising:

calculating the at least one harmonic signal according to a frequency component of the second digital input signal.

12. The signal processing method of claim 10 , wherein the step of deleting the harmonic component of the first digital input signal by using the at least one harmonic signal to generate the output signal comprises:

directly subtracting the at least one harmonic signal from the first digital input signal to generate the output signal.

13. The signal processing method of claim 10 , wherein the step of generating the at least one harmonic signal according to the second digital input signal comprises:

calculating at least one initial harmonic signal according to the second digital input signal; and

using a gain adjustment circuit to adjust a gain of the at least one initial harmonic signal to generate the at least one harmonic signal.

14. The signal processing method of claim 13 , wherein the step of generating the at least one harmonic signal according to the second digital input signal comprises:

using the gain adjustment circuit and a phase adjustment circuit to adjust the gain and a phase of the at least one initial harmonic signal to generate the at least one harmonic signal.

15. The signal processing method of claim 14 , further comprising:

adjusting a gain setting of the gain adjustment circuit and phase adjustment amount of the phase adjustment circuit according to the output signal.

16. The signal processing method of claim 15 , wherein the step of adjusting the gain setting of the gain adjustment circuit and the phase adjustment amount of the phase adjustment circuit according to the output signal comprises:

adjusting the gain setting of the gain adjustment circuit and the phase adjustment amount of the phase adjustment circuit according to a strength of a harmonic component of the output signal, to make the strength of the harmonic component of the output signal be lower than a threshold value.

17. The signal processing method of claim 13 , further comprising:

delaying a phase of the first digital input signal for the generation of the output circuit.

18. The signal processing method of claim 13 , wherein the at least one initial harmonic signal comprises a second harmonic and a third harmonic.