Apparatus and method with in-memory delay dependent processing
An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.
1. An in-memory processing apparatus, the apparatus comprising:
a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines;
voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums;
a time-digital converter configured to perform time-digital conversion at the second time points; and
sampling resistors connected to the column lines,
wherein the sampling voltages are applied to the sampling resistors.
2. The apparatus of claim 1 , wherein the voltage controlled delay circuits are configured to determine the delay times in proportion to the magnitudes of the sampling voltages.
3. The apparatus of claim 1 , wherein the voltage controlled delay circuits are current-starved types including transistors to which the sampling voltages are applied and inverters to which the start signal is input.
4. The apparatus of claim 1 , wherein the voltage controlled delay circuits include biases connected to the column lines and configured to apply the sampling voltages, current-starved delay elements to which the start signals are input, and buffers configured to output the stop signals.
5. The device of claim 1 , wherein
the sampling resistors are connected in series to the column lines, and
the voltage controlled delay circuits are connected in parallel to the sampling resistors.
6. The apparatus of claim 1 , wherein values of the sampling voltages are determined based on composite resistances of resistance values of the memory cell groups and resistance values of the sampling resistors.
7. The apparatus of claim 1 , further comprising a driver configured to input the input signals to the memory cell array at a third time point synchronized with the first time point.
8. The apparatus of claim 1 , wherein the time-digital converter is configured to
reset a counter at the first time point, and
output counting values as digital values at the second time points.
9. The apparatus of claim 8 , wherein the time-digital converter includes an oscillator configured to generate a pulse at the first time point and the counter configured to count the pulse.
10. The apparatus of claim 8 , wherein the time-digital converter includes flip-flops configured to latch the counting values at the second time point.
11. A computing apparatus comprising:
a host processor;
a memory device; and
an in-memory processing device comprising:
a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines;
voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums;
a time-digital converter configured to perform time-digital conversion at the second time points; and
sampling resistors connected to the column lines,
wherein the sampling voltages are applied to the sampling resistors.
12. The apparatus of claim 11 , wherein the voltage controlled delay circuits are configured to determine the delay times in proportion to the magnitudes of the sampling voltages.
13. The apparatus of claim 11 , wherein the voltage controlled delay circuits are current-starved types including transistors to which the sampling voltages are input and inverters to which the start signal is input.
14. The apparatus of claim 11 , wherein the voltage controlled delay circuits include biases connected to the column lines and configured to apply the sampling voltages, current-starved delay elements to which the start signals are input, and buffers configured to output the stop signals.
15. The apparatus of claim 11 , wherein the time-digital converter is configured to
reset a counter at the first time point, and
output counting values as digital values at the second time points.
16. The apparatus of claim 11 , wherein the memory device stores instructions that, when executed by the host processor, configure the host processor to control the in-memory processing device to perform the generating of the current sums, the outputting of the stop signals, and the performing of the time-digital conversion.
17. An in-memory processing method, the method comprising:
inputting input signals to memory cell groups through row lines of a memory cell array;
applying sampling voltages corresponding to current sums of column currents flowing through column lines of the memory cell array to voltage controlled delay circuits connected to the column lines;
inputting a start signal to the voltage controlled delay circuits at a first time point;
outputting stop signals at second time points delayed by delay times determined based on magnitudes of the sampling voltages; and
performing time-digital conversion at the second time points,
wherein sampling resistors are connected to the column lines, and
wherein the method further comprises determining the sampling voltages based on composite resistances of resistance values of the memory cell groups and resistance values of the sampling resistors.
18. The method of claim 17 , further comprising resetting a counter at the first time point, and outputting counting values as digital values at the second time points.
19. The method of claim 18 , further comprising outputting, based on the output counting values, an output digital value corresponding to a MAC operation result of a neural network.
20. An in-memory processing apparatus, the apparatus comprising:
a memory cell array comprising memory cell groups each corresponding to a respective column line and configured to generate a current sum of column currents flowing through the respective column line in response to input signals applied through row lines;
voltage controlled delay circuits each corresponding to a respective column line and configured to output, in response to an input of a start signal at a first time point, a stop signal at second time point delayed by a delay time determined based on a magnitude of an applied sampling voltage corresponding to a respective one of the current sums;
a time-digital converter configured to, based on the stop signals, perform time-digital conversion at the second time points; and
sampling resistors connected to the column lines,
wherein the sampling voltages are applied to the sampling resistors.
21. The apparatus of claim 20 , wherein the time-digital converter comprises:
an oscillator configured to generate a counting pulse starting from the first time point, in response to receiving the start signal;
a counter configured to generate counting values of the counting pulse in response to the generating of the counting pulse; and
flip-flops each corresponding to a respective one of the column lines and configured to output a counting value of the generated counting values corresponding to a respective second time point, in response to receiving a stop signal of the stop signals from a respective one of the voltage controlled delay circuits.