Silicon rich nitride layer between a plurality of semiconductor layers
According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
1. A semiconductor device, comprising:
a first electrode;
a second electrode, a direction from the second electrode toward the first electrode being aligned with a first direction;
a third electrode, a position in the first direction of the third electrode being between a position in the first direction of the first electrode and a position in the first direction of the second electrode;
a first semiconductor layer including Al x1 Ga 1-x1 N (0≤x 1 ≤1), the first semiconductor layer including first to fifth partial regions, a direction from the fourth partial region toward the first electrode, a direction from the fifth partial region toward the second electrode, and a direction from the third partial region toward the third electrode being aligned with a second direction crossing the first direction, the first partial region being between the fourth partial region and the third partial region in the first direction, the second partial region being between the third partial region and the fifth partial region in the first direction;
a nitride layer including silicon and nitrogen, a ratio Si/N of a concentration of silicon (Si) in the nitride layer to a concentration of nitrogen (N) in the nitride layer being not less than 0.68 and not more than 0.72, the nitride layer including a first nitride region and a second nitride region;
a second semiconductor layer including Al x2 Ga 1-x2 N (0<x 2 ≤1), the second semiconductor layer including a first semiconductor region and a second semiconductor region, the first semiconductor region being provided between the first partial region and the first nitride region in the second direction and contacting the first nitride region, the second semiconductor region being provided between the second partial region and the second nitride region in the second direction and contacting the second nitride region;
an oxide layer including silicon and oxygen, a concentration of nitrogen in the oxide layer being lower than a concentration of nitrogen in the nitride layer, the oxide layer including first to third oxide regions, at least a portion of the first nitride region being provided between the first oxide region and the second semiconductor region, at least a portion of the second nitride region being provided between the second oxide region and the second semiconductor region, the third oxide region being provided between the third partial region and the third electrode and contacting the third partial region and the third electrode; and
a first intermediate region provided between the first nitride region and the first oxide region,
the first intermediate region including one of a first material or a second material, the first material including silicon, oxygen, and nitrogen, the second material including aluminum and nitrogen.
2. The device according to claim 1 , wherein a first thickness along the second direction of the first nitride region is 10 nm or less.
3. The device according to claim 2 , wherein the first thickness is 0.2 nm or more.
4. The device according to claim 1 , wherein the ratio Si/N is not less than 0.69 and not more than 0.71.
5. The device according to claim 1 , wherein
at least a portion of the first nitride region contacts the first oxide region, and
at least a portion of the second nitride region contacts the second oxide region.
6. The device according to claim 1 , wherein at least a portion of the third oxide region is between the first semiconductor region and the second semiconductor region in the first direction.
7. The device according to claim 1 , wherein a portion of the third oxide region is between the first partial region and the second partial region in the first direction.
8. The device according to claim 1 , wherein
a portion of the third oxide region is between at least a portion of the first semiconductor region and at least a portion of the second semiconductor region in the first direction.
9. The device according to claim 1 , wherein
the third electrode includes first to third electrode regions,
a position in the first direction of the third electrode region is between a position in the first direction of the first electrode region and a position in the first direction of the second electrode region,
the oxide layer further includes a fourth oxide region and a fifth oxide region,
the nitride layer further includes a third nitride region and a fourth nitride region,
the fourth oxide region is between the third nitride region and the first electrode region in the second direction,
the fifth oxide region is between the fourth nitride region and the second electrode region in the second direction, and
the third oxide region is provided between the third partial region and the third electrode region and contacts the third partial region and the third electrode region.
10. The device according to claim 9 , wherein a thickness along the second direction of the third oxide region is thinner than a thickness along the second direction of the fourth oxide region and thinner than a thickness along the second direction of the fifth oxide region.
11. The device according to claim 10 , wherein an absolute value of a difference between the thickness along the second direction of the third oxide region and the thickness along the second direction of the fourth oxide region is not less than 30 nm and not more than 100 nm.
12. The device according to claim 10 , wherein
the thickness along the second direction of the fourth oxide region is thicker than a thickness along the second direction of the first oxide region, and
the thickness along the second direction of the fifth oxide region is thicker than a thickness along the second direction of the second oxide region.
13. The device according to claim 9 , wherein a length along the first direction of the first electrode region is 5 μm or less.
14. The device according to claim 9 , wherein a length along the first direction of the first electrode region is not less than 0.035 times and not more than 0.35 times a length along the first direction between the first electrode region and the first electrode.
15. The device according to claim 1 , wherein a concentration of a bond of silicon and hydrogen in the nitride layer is 6×10 21 cm −3 or less.
16. The device according to claim 1 , wherein a concentration of hydrogen in the third oxide region is 2×10 19 cm −3 or less.
17. The device according to claim 1 , wherein
the first electrode is a drain electrode,
the second electrode is a source electrode, and
the third electrode is a gate electrode.
18. The device according to claim 1 , wherein the composition ratio x 1 is not less than 0 and not more than 0.2.
19. The device according to claim 18 , wherein the composition ratio x 2 is not less than 0.05 and not more than 0.35.
20. A semiconductor device, comprising:
a first electrode;
a second electrode, a direction from the second electrode toward the first electrode being aligned with a first direction;
a third electrode, a position in the first direction of the third electrode being between a position in the first direction of the first electrode and a position in the first direction of the second electrode;
a first semiconductor layer including Al x1 Ga 1-x1 N (0≤x 1 ≤1), the first semiconductor layer including first to fifth partial regions, a direction from the fourth partial region toward the first electrode, a direction from the fifth partial region toward the second electrode, and a direction from the third partial region toward the third electrode being aligned with a second direction crossing the first direction, the first partial region being between the fourth partial region and the third partial region in the first direction, the second partial region being between the third partial region and the fifth partial region in the first direction;
a nitride layer including silicon and nitrogen, a ratio Si/N of a concentration of silicon (Si) in the nitride layer to a concentration of nitrogen (N) in the nitride layer being not less than 0.68 and not more than 0.72, the nitride layer including a first nitride region and a second nitride region;
a second semiconductor layer including Al x2 Ga 1-x2 N (0<x 2 ≤1), the second semiconductor layer including a first semiconductor region and a second semiconductor region, the first semiconductor region being provided between the first partial region and the first nitride region in the second direction and contacting the first nitride region, the second semiconductor region being provided between the second partial region and the second nitride region in the second direction and contacting the second nitride region; and
an oxide layer including silicon and oxygen, a concentration of nitrogen in the oxide layer being lower than a concentration of nitrogen in the nitride layer, the oxide layer including first to third oxide regions, at least a portion of the first nitride region being provided between the first oxide region and the second semiconductor region, at least a portion of the second nitride region being provided between the second oxide region and the second semiconductor region, the third oxide region being provided between the third partial region and the third electrode and contacting the third partial region and the third electrode,
wherein
the third electrode includes first to third electrode regions,
a position in the first direction of the third electrode region is between a position in the first direction of the first electrode region and a position in the first direction of the second electrode region,
the oxide layer further includes a fourth oxide region and a fifth oxide region,
the nitride layer further includes a third nitride region and a fourth nitride region,
the fourth oxide region is between the third nitride region and the first electrode region in the second direction,
the fifth oxide region is between the fourth nitride region and the second electrode region in the second direction, and
the third oxide region is provided between the third partial region and the third electrode region and contacts the third partial region and the third electrode region,
wherein a thickness along the second direction of the third oxide region is thinner than a thickness along the second direction of the fourth oxide region and thinner than a thickness along the second direction of the fifth oxide region.
21. The device according to claim 20 , wherein
the thickness along the second direction of the fourth oxide region is thicker than a thickness along the second direction of the first oxide region, and
the thickness along the second direction of the fifth oxide region is thicker than a thickness along the second direction of the second oxide region.
22. The device according to claim 20 , wherein the composition ratio x 1 is not less than 0 and not more than 0.2.
23. The device according to claim 22 , wherein the composition ratio x 2 is not less than 0.05 and not more than 0.35.
24. The device according to claim 20 , wherein the composition ratio x 1 is not less than 0 and not more than 0.2.
25. The device according to claim 24 , wherein the composition ratio x 2 is not less than 0.05 and not more than 0.35.
26. A semiconductor device, comprising:
a first electrode;
a second electrode, a direction from the second electrode toward the first electrode being aligned with a first direction;
a third electrode, a position in the first direction of the third electrode being between a position in the first direction of the first electrode and a position in the first direction of the second electrode;
a first semiconductor layer including Al x1 Ga 1-x1 N (0≤x 1 ≤1), the first semiconductor layer including first to fifth partial regions, a direction from the fourth partial region toward the first electrode, a direction from the fifth partial region toward the second electrode, and a direction from the third partial region toward the third electrode being aligned with a second direction crossing the first direction, the first partial region being between the fourth partial region and the third partial region in the first direction, the second partial region being between the third partial region and the fifth partial region in the first direction;
a nitride layer including silicon and nitrogen, a ratio Si/N of a concentration of silicon (Si) in the nitride layer to a concentration of nitrogen (N) in the nitride layer being not less than 0.68 and not more than 0.72, the nitride layer including a first nitride region and a second nitride region;
a second semiconductor layer including Al x2 Ga 1-x2 N (0<x 2 ≤1), the second semiconductor layer including a first semiconductor region and a second semiconductor region, the first semiconductor region being provided between the first partial region and the first nitride region in the second direction and contacting the first nitride region, the second semiconductor region being provided between the second partial region and the second nitride region in the second direction and contacting the second nitride region; and
an oxide layer including silicon and oxygen, a concentration of nitrogen in the oxide layer being lower than a concentration of nitrogen in the nitride layer, the oxide layer including first to third oxide regions, at least a portion of the first nitride region being provided between the first oxide region and the second semiconductor region, at least a portion of the second nitride region being provided between the second oxide region and the second semiconductor region, the third oxide region being provided between the third partial region and the third electrode and contacting the third partial region and the third electrode,
wherein
the third electrode includes first to third electrode regions,
a position in the first direction of the third electrode region is between a position in the first direction of the first electrode region and a position in the first direction of the second electrode region,
the oxide layer further includes a fourth oxide region and a fifth oxide region,
the nitride layer further includes a third nitride region and a fourth nitride region,
the fourth oxide region is between the third nitride region and the first electrode region in the second direction,
the fifth oxide region is between the fourth nitride region and the second electrode region in the second direction, and
the third oxide region is provided between the third partial region and the third electrode region and contacts the third partial region and the third electrode region,
wherein a length along the first direction of the first electrode region is not less than 0.035 times and not more than 0.35 times a length along the first direction between the first electrode region and the first electrode.