Selective boot sequence controller for resilient storage memory

1. A storage device for booting a host computing device, the storage device comprising:

an input/output interface configured to connect to the host computing device;

a first storage memory controller;

a first storage memory region coupled to and accessible via the first storage memory controller;

a second storage memory controller;

a second storage memory region coupled to and accessible via the second storage memory controller; and

a resilient boot controller communicatively coupling the input/output interface to the first storage memory region through the first storage memory controller and to the second storage memory region through the second storage memory controller, the resilient boot controller being configured to

store boot code in the first storage memory region,

prevent write access by the host computing device through the first storage memory controller to the first storage memory region,

detect a reset of the host computing device through the input/output interface,

copy at least a portion of the boot code from the first storage memory region to the second storage memory region, responsive to detection of the reset of the host computing device, and

enable read access of the copied boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the copy operation.

2. The storage device of claim 1 wherein the resilient boot controller is further configured to

enable read access of the boot code by the host computing device through the first storage memory controller of the first storage memory region during a first time period of the boot sequence, responsive to detection the reset of the host computing device through the input/output interface, and

switch read access by the host computing device from the first storage memory bank to the second storage memory bank.

3. The storage device of claim 1 wherein the boot code stored in the first storage memory region includes a storage memory switch instruction and the resilient boot controller is further configured to

enable read access of the boot code by the host computing device through the first storage memory controller of the first storage memory region, responsive to detection the reset of the host computing device through the input/output interface,

detect execution of the storage memory switch instruction by the host computing device, and

switch read access by the host computing device from the first storage memory region to the second storage memory region, responsive to execution of the storage memory switch instruction by the host computing and the copy operation.

4. The storage device of claim 1 wherein the resilient boot controller is further configured to

enable read access of the boot code by the host computing device through the first storage memory controller of the first storage memory region, responsive to detection the reset of the host computing device through the input/output interface,

detect satisfaction of a storage memory switch condition, and

switch read access by the host computing device from the first storage memory region to the second storage memory region, responsive to satisfaction of a storage memory switch condition and the copy operation.

5. The storage device of claim 1 , further comprising:

a security protection module device communicatively coupled to the resilient boot controller, the security protection module device being configured to cryptographically evaluate a code update package received from the host computing device, the resilient boot controller being further configured to

update the boot code stored in the first storage memory controller with the code update package, responsive to a cryptographic evaluation that the code update package satisfies a cryptographic update condition, and

prevent updating of the boot code stored in the first storage memory controller, responsive to a cryptographic evaluation that the code update package fails to satisfy a cryptographic update condition.

6. The storage device of claim 5 , wherein the resilient boot controller is further configured to update the boot code by switching access by the host computing device from the second storage memory region to the first storage memory region and enabling write access of the code update package to the first storage memory region, prior to a subsequent reset of the host computing system.

7. The storage device of claim 6 , wherein the security protection module device is further configured to perform the cryptographic evaluation to determine whether the code update package satisfies a cryptographic update condition, prior to a subsequent reset of the host computing system.

8. The storage device of claim 5 , wherein the resilient boot controller is further configured to update the boot code by switching access by the host computing device from the second storage memory region to the first storage memory region and enabling write access of the code update package to the first storage memory region, after a subsequent reset of the host computing system.

9. The storage device of claim 8 , wherein the security protection module device is further configured to perform the cryptographic evaluation to determine whether the code update package satisfies a cryptographic update condition, after the subsequent reset of the host computing system.

10. The storage device of claim 8 , wherein the code update package is stored in the second storage memory region, prior to the subsequent reset of the host computing system.

11. A method of booting a host computing device from a storage device, the storage device including an input/output interface configured to connect to the host computing device, a first storage memory region having a first storage memory controller, and a second storage memory region having a second storage memory controller, the method comprising:

storing boot code in the first storage memory region;

preventing write access by the host computing device through the first storage memory controller to the first storage memory region;

detecting a reset of the host computing device through the input/output interface;

copying at least a portion of the boot code from the first storage memory region to the second storage memory region, responsive to detection of the reset of the host computing device; and

enabling read access of the copied boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the copy operation.

12. The method of claim 11 , further comprising:

enabling read access of the boot code by the host computing device through the first storage memory controller of the first storage memory region during a first time period of the boot sequence, responsive to detection the reset of the host computing device through the input/output interface; and

switching read access by the host computing device from the first storage memory region to the second storage memory region.

13. The method of claim 11 , wherein the boot code stored in the first storage memory region includes a storage memory switch instruction and further comprising:

enabling read access of the boot code by the host computing device through the first storage memory controller of the first storage memory region, responsive to detection the reset of the host computing device through the input/output interface,

detecting execution of the storage memory switch instruction by the host computing device, and

switching read access by the host computing device from the first storage memory region to the second storage memory region, responsive to execution of the storage memory switch instruction by the host computing and the copy operation.

14. The method of claim 11 , further comprising:

enabling read access of the boot code by the host computing device through the first storage memory controller of the first storage memory region, responsive to detection the reset of the host computing device through the input/output interface,

detecting satisfaction of a storage memory switch condition, and

switching read access by the host computing device from the first storage memory region to the second storage memory region, responsive to satisfaction of a storage memory switch condition and the copy operation.

15. The method of claim 11 , further comprising:

cryptographically evaluating a code update package received from the host computing device;

updating the boot code stored in the first storage memory controller with the code update package, responsive to a cryptographic evaluation that the code update package satisfies a cryptographic update condition; and

preventing update of the boot code stored in the first storage memory controller, responsive to the cryptographic evaluation that the code update package fails to satisfy a cryptographic update condition.

16. The method of claim 15 , further comprising:

updating the boot code by switching access by the host computing device from the second storage memory region to the first storage memory region, prior to a subsequent reset of the host computing system; and

enabling write access of the code update package to the first storage memory region, prior to a subsequent reset of the host computing system.

17. The method of claim 16 , further comprising:

performing the cryptographic evaluation to determine whether the code update satisfies a cryptographic update condition, prior to a subsequent reset of the host computing system.

18. The method of claim 15 , further comprising:

updating the boot code by switching access by the host computing device from the second storage memory region to the first storage memory region, after a subsequent reset of the host computing system; and

enabling write access of the code update package to the first storage memory region, after a subsequent reset of the host computing system.

19. The method of claim 18 , further comprising:

performing the cryptographic evaluation to determine whether the code update satisfies a cryptographic update condition, after the subsequent reset of the host computing system.

20. A storage device for booting a host computing device using boot code in a boot sequence, the storage device comprising:

an input/output interface configured to connect to the host computing device;

a first storage memory controller;

a first storage memory region coupled to and accessible via the first storage memory controller;

a second storage memory controller;

a second storage memory region coupled to and accessible via the second storage memory controller; and

a resilient boot controller communicatively coupling the input/output interface to the first storage memory region through the first storage memory controller and to the second storage memory region through the second storage memory controller, the resilient boot controller being configured to

store a first portion of the boot code in the first storage memory region,

store a second portion of the boot code in the second storage memory region, wherein execution of the second portion of the boot code follows the first portion of the boot code in the boot sequence,

detect a reset of the host computing device through the input/output interface,

enable read access and prevent write access to the first portion of the boot code by the host computing device through the first storage memory controller of the first storage memory region and prevent read and write access to the second portion of the boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the reset operation, and

enable read and write access to the second portion of the boot code by the host computing device through the second storage memory controller of the second storage memory region and prevent read and write access to the first portion of the boot code by the host computing device through the first storage memory controller of the first storage memory region, responsive to execution of the first portion of the boot code in the boot sequence by the host computing device.

21. The method of claim 11 , wherein:

the input/output interface is configured to connect to the first storage memory region having the first storage memory controller and the second storage memory region having the second storage memory controller via a resilient boot controller operable to perform one or more of the operations of storing boot code, preventing write access, detecting a reset, and enabling read access.

22. The storage device of claim 1 , wherein the enablement of read access of the copied boot code includes enabling read access of the copied boot code by the host computing device to store the copied boot code in memory of the host computing device.

23. The storage device of claim 1 , wherein the input/output interface is configured to connect the storage device to the host computing device.