Time-to-digital conversion circuit and source driver including the same
The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.
1. A time-to-digital conversion circuit comprising:
a first time-to-digital conversion circuit enabled when a first phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the first phase difference; and
a second time-to-digital conversion circuit enabled when the first phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the first phase difference.
2. The time-to-digital conversion circuit of claim 1 , wherein the second time-to-digital conversion circuit comprises:
a first time-to-digital converter configured to output a first output signal corresponding to the first phase difference; and
a second time-to-digital converter configured to output a second output signal corresponding to a second phase difference between the recovery clock signal and a first clock signal,
wherein the first clock signal has the preset second phase difference from the recovery clock signal.
3. The time-to-digital conversion circuit of claim 2 , wherein the second phase difference is set identically with the reference phase difference.
4. The time-to-digital conversion circuit of claim 2 , wherein the second time-to-digital conversion circuit converts the first output signal into the second digital signal when a value of the first output signal is equal to or smaller than a value of the second output signal.
5. The time-to-digital conversion circuit of claim 2 , wherein the second time-to-digital conversion circuit further comprises:
a comparator configured to compare the first output signal and the second output signal and output a comparison signal based on a result of the comparison;
a flip-flop array configured to update the first output signal and output the updated signal as a flip-flop signal in response to an enabled comparison signal and to output the flip-flop signal that maintains a previous value in response to a disabled comparison signal; and
an encoder configured to convert the flip-flop signal into the second digital signal.
6. The time-to-digital conversion circuit of claim 2 , wherein the second time-to-digital conversion circuit outputs the second digital signal that maintains a previous value when a value of the first output signal is greater than a value of the second output signal.
7. The time-to-digital conversion circuit of claim 1 , wherein the second time-to-digital conversion circuit outputs the second digital signal that maintains a previous value when the clock of the input signal is not recognized.
8. The time-to-digital conversion circuit of claim 1 , further comprising a multiplexer configured to select one of the first digital signal and the second digital signal and output the selected signal, in response to a coarse lock signal enabled or disabled depending on whether the first phase difference is equal to or smaller than the reference phase difference.
9. The time-to-digital conversion circuit of claim 8 , wherein the multiplexer selects the first digital signal when the first phase difference is greater than the reference phase difference and selects the second digital signal when the phase difference is equal to or smaller than the reference phase difference.
10. A source driver comprising:
a clock and data recovery circuit configured to generate a recovery clock signal and recovery data from an input signal by using a time-to-digital conversion circuit; and
a data driving circuit configured to convert the recovery data into a data voltage and provide the data voltage to a display panel,
wherein the time-to-digital conversion circuit comprises:
a first time-to-digital conversion circuit enabled when a first phase difference between a clock of the input signal and the recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the first phase difference; and
a second time-to-digital conversion circuit enabled when the first phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the first phase difference.
11. The source driver of claim 10 , wherein the second time-to-digital conversion circuit comprises:
a first time-to-digital converter configured to output a first output signal corresponding to the first phase difference; and
a second time-to-digital converter configured to output a second output signal corresponding to a second phase difference between the recovery clock signal and a first clock signal,
wherein the first clock signal has the second phase difference from the recovery clock signal.
12. The source driver of claim 11 , wherein the second phase difference is set identically with the reference phase difference.
13. The source driver of claim 11 , wherein the second time-to-digital conversion circuit converts the first output signal into the second digital signal when a value of the first output signal is equal to or smaller than a value of the second output signal.
14. The source driver of claim 11 , wherein the second time-to-digital conversion circuit further comprises:
a comparator configured to compare the first output signal and the second output signal and output a comparison signal based on a result of the comparison;
a flip-flop array configured to update the first output signal and output the updated signal as a flip-flop signal in response to an enabled comparison signal and to output the flip-flop signal that maintains a previous value in response to a disabled comparison signal; and
an encoder configured to convert the flip-flop signal into the second digital signal and output the second digital signal to a digital loop filter.
15. The source driver of claim 11 , wherein the second time-to-digital conversion circuit outputs the second digital signal that maintains a previous value when a value of the first output signal is greater than a value of the second output signal.
16. The source driver of claim 10 , wherein the second time-to-digital conversion circuit outputs the second digital signal that maintains a previous value when the clock of the input signal is not recognized.
17. The source driver of claim 10 , further comprising a multiplexer configured to select one of the first digital signal and the second digital signal and output the selected signal, in response to a coarse lock signal enabled or disabled depending on whether the first phase difference is equal to or smaller than the reference phase difference.
18. The source driver of claim 17 , wherein the multiplexer selects the first digital signal when the first phase difference is greater than the reference phase difference and selects the second digital signal when the first phase difference is equal to or smaller than the reference phase difference.