Top electrode via with low contact resistance

1. A memory device, comprising:

a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate;

a data storage structure disposed over the bottom electrode;

a first top electrode layer disposed over the data storage structure;

a second top electrode layer on the first top electrode layer, wherein the second top electrode layer is less susceptible to oxidation than the first top electrode layer;

a top electrode via over and electrically coupled to the second top electrode layer, wherein the top electrode via extends from over a top surface of the second top electrode layer to below the top surface of the second top electrode layer; and

wherein the top electrode via is separated from the first top electrode layer by the second top electrode layer and wherein the second top electrode layer has a first non-zero thickness directly below the top electrode via and a second thickness outside of the top electrode via, the second thickness greater than the first non-zero thickness.

2. The memory device of claim 1 , further comprising:

a top electrode oxide disposed between the top electrode via and the second top electrode layer.

3. The memory device of claim 2 , further comprising:

a first oxide disposed along one or more sidewalls of the first top electrode layer, wherein the first oxide has a greater thickness than the top electrode oxide.

4. The memory device of claim 1 , wherein the second top electrode layer comprises titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, or hafnium nitride.

5. The memory device of claim 1 , wherein the first top electrode layer comprises tantalum and the second top electrode layer comprises titanium nitride.

6. The memory device of claim 1 , wherein the second top electrode layer has a thickness in a range of between approximately 20 Angstroms (Å) and approximately 300 Å.

7. The memory device of claim 1 , wherein the second top electrode layer has a corrosion potential of greater than or equal to approximately −0.4V.

8. The memory device of claim 1 , wherein the second top electrode layer has a boiling point in a fluorine gas of greater than approximately 1500° C.

9. The memory device of claim 1 , wherein the second top electrode layer comprises a material that utilizes a Gibbs free energy of greater than −600 kJ/mol to form an oxide.

10. A memory device, comprising:

a bottom electrode disposed over a substrate;

a data storage structure disposed on the bottom electrode;

a first top electrode layer disposed on the data storage structure;

a second top electrode layer disposed on the first top electrode layer;

a top electrode via disposed on the second top electrode layer, wherein the second top electrode layer is separated from the top electrode via by a top electrode oxide; and

wherein the first top electrode layer comprises a first material that utilizes a first Gibbs free energy to form an oxide of the first material and the second top electrode layer comprises a second material that utilizes a second Gibbs free energy to form an oxide of the second material, the second Gibbs free energy being larger than the first Gibbs free energy.

11. The memory device of claim 10 , wherein the second Gibbs free energy is greater than −600 kJ/mol.

12. The memory device of claim 10 , wherein the top electrode via extends to a non-zero distance below a top of the second top electrode layer.

13. The memory device of claim 10 , wherein the first top electrode layer is separated from the top electrode via by the second top electrode layer.

14. The memory device of claim 10 , wherein a first oxide is arranged along outer edges of the first top electrode layer and a second oxide is arranged along outer edges of the second top electrode layer, the first oxide having a greater thickness than the second oxide.

15. A memory device, comprising:

a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate;

a data storage structure disposed over the bottom electrode;

a first top electrode layer disposed over the data storage structure;

a second top electrode layer on the first top electrode layer, wherein the second top electrode layer is less susceptible to oxidation than the first top electrode layer and wherein the second top electrode layer has a thickness in a range of between approximately 20 Angstroms (Å) and approximately 300 Å;

sidewall spacers arranged along opposing sides of the first top electrode layer and the second top electrode layer; and

a top electrode via over and electrically coupled to the second top electrode layer.

16. The memory device of claim 15 , wherein the second top electrode layer comprises titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, or hafnium nitride.

17. The memory device of claim 15 , wherein the top electrode via has a bottommost surface that is below a top of the second top electrode layer.

18. The memory device of claim 15 , wherein the second top electrode layer comprises titanium nitride.

19. The memory device of claim 15 , further comprising:

a capping layer arranged between the data storage structure and the first top electrode layer.

20. The memory device of claim 15 , wherein a first oxide is arranged along outer edges of the first top electrode layer and a second oxide is arranged along outer edges of the second top electrode layer, the first oxide having a greater thickness than the second oxide.