IP Library Granted Patent US 11,528,126
Granted Patent B2
US 11,528,126 · App. 17/176,447 · Granted Dec 13, 2022

Interface for revision-limited memory

Inventors: Eunchan Kim (San Jose, CA); Michael Stefano Fritz Schaffner (Campbell, CA); Timothy Jay Chen (Pleasanton, CA); Christopher Gori (San Francisco, CA); Ziv Hershman (Givat Schmuel, IL); Miguel Angel Osorio (El Dorado Hills, CA)
Assignee: Google LLC
H04L9/0618G06F1/10G06F3/0622G06F3/0656G06F3/0659G06F3/0673G11C29/38G11C29/44H04L9/0869H04L2209/16
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Quick Facts
Patent No.
US 11,528,126
App. No.
17/176,447
Granted
Dec 13, 2022
Kind
B2
Abstract

This document includes techniques, apparatuses, and systems related to an interface for revision-limited memory, which can improve various computing aspects and performance. In aspects, confidentiality, integrity, and availability may be ensured while increasing the performance of revision-limited memory. In this example, the techniques also enable the digital computing device to interact with information related to the revision-limited memory.

Claims (62)

1. A method for interfacing with revision-limited memory, the method comprising:

translating a generic command indicative of an operation associated with the revision-limited memory to an access port command indicative of the operation for the revision-limited memory;

sending the access port command to the revision-limited memory instructing the revision-limited memory to execute the operation;

receiving an output based on the access port command, the output including revision-limited data from the revision-limited memory; and

dividing the revision-limited data according to a bit width associated with obfuscating circuitry associated with the revision-limited memory.

2. The method of claim 1 , wherein the operation is a built-in self-test of the revision-limited memory and the generic command defines the built-in self-test, the built-in self-test configured to scan a portion of the revision-limited memory for erroneous bits, and wherein receiving the output comprises an error based on the built-in self-test.

3. The method of claim 1 , further comprising sending write data with the access port command to the revision-limited memory, the write data sized according to a bit width of obfuscating circuitry associated with the revision-limited memory.

4. The method of claim 1 , further comprising dividing user data into chunks according to a bit width associated with obfuscating circuitry associated with the revision-limited memory.

5. The method of claim 4 , further comprising obfuscating the chunks and sending the obfuscated chunks with the access port command.

6. The method of claim 1 , further comprising:

reading from the revision-limited memory;

sending a clock signal to the revision-limited memory based on two glitchless clock multiplexers; and

disabling the clock signal based on data defined in a life cycle partition of the revision-limited memory.

7. A method comprising:

receiving an address space of a revision-limited memory, the address space:

defined by a control-status register mapped to the address space; and

based on a partition of the revision-limited memory;

accessing the address space within the partition of the revision-limited memory to read content from the partition;

providing first data based on the content to the control-status register;

receiving a second address space of the revision-limited memory, the second address space:

defined by the control-status register memory mapped to the second address space; and

based on a second partition of the revision-limited memory;

accessing the second address space within the second partition of the revision-limited memory to read second content from the partition; and

providing second data based on the second content to the control-status register.

8. The method of claim 7 , wherein accessing the address space is based on an generic command, and accessing the second address space is based on a second generic command.

9. The method of claim 7 , wherein providing the second data further comprises outputting the second data to an output register and providing the first data further comprises outputting a digest of the first data to the output register.

10. The method of claim 7 , wherein providing the first data further comprises:

deobfuscating the first data into unobfuscated first data;

buffering the unobfuscated first data; and

outputting a digest of the unobfuscated first data to an output register, and

wherein providing the second data further comprises:

deobfuscating the second data into unobfuscated second data;

buffering the unobfuscated second data; and

outputting a second digest of the unobfuscated second data to the output register.

11. The method of claim 7 , further comprising:

locking an access interface to the revision-limited memory according to a lock byte based on a digest of data stored in the address space.

12. The method of claim 7 , wherein the first data is first partition data, the method further comprising:

buffering the first partition data into first buffered partition data;

calculating a digest of the buffered first partition data;

storing the digest of the buffered first partition data;

calculating a second digest of the buffered first partition data; and

resetting hardware outputs of a controller to defaults based on the digest and the second digest.

13. The method of claim 7 , wherein the first data is first partition data, the method further comprising:

repeating an operation associated with the first partition data to provide second data associated with the address space;

comparing the second data to the first partition data; and

resetting hardware outputs of a controller to defaults based on the comparison.

14. The method of claim 7 , further comprising:

maintaining buffered data associated with multiple partitions of the revision-limited memory based on the revision-limited memory that includes the first data;

writing to a second address space of the revision-limited memory; and

maintaining the buffered data until a reset of the revision-limited memory.

15. The method of claim 7 , wherein data of the revision-limited memory is organized according to predetermined address spaces defined as partitions that include the partition of the revision-limited memory, the partitions having a quantity greater than one, the method further comprising:

buffering the data corresponding to a subset of the partitions, the subset being less than the quantity.

16. A method comprising:

generating an obfuscating key based on an initialization vector, a key seed, a first number from a cryptographically secure number-generator, and a hardware constant associated with a revision-limited memory;

receiving data associated with an address space of the revision-limited memory;

generating obfuscated data based on the data according to the obfuscating key;

writing the obfuscated data to the address space; and

receiving an indication of a successful write to the address space.

17. The method of claim 16 , wherein the obfuscating key is a first key portion of the obfuscating key, the method further comprising:

receiving a second number from the cryptographically secure number-generator; and

generating a second key portion of the obfuscating key based on the initialization vector, the key seed, the first number, and the hardware constant.

18. The method of claim 16 , wherein the key seed is stored on the revision-limited memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2021
From: KIM, EUNCHAN; SCHAFFNER, MICHAEL STEFANO FRITZ; CHEN, TIMOTHY JAY; GORI, CHRISTOPHER; HERSHMAN, ZIV; OSORIO, MIGUEL ANGEL
To: GOOGLE LLC
Reel/Frame 055271/0691 →
Continuity (1)
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