Source/drain contacts and methods of forming same
A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.
1. A device comprising:
a device layer comprising a first transistor and a second transistor;
a first interconnect structure on a front-side of the device layer; and
a second interconnect structure on a backside of the device layer, the second interconnect structure comprising:
a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor;
a metal contact extending through the first dielectric layer to a second source/drain region of the second transistor; and
a first conductive line electrically connected to the second source/drain region of the second transistor through the metal contact.
2. The device of claim 1 , wherein the first conductive line is a power supply line or an electrical ground line.
3. The device of claim 1 further comprising a dielectric liner between the first dielectric layer and the device layer, wherein the metal contact extends through the dielectric liner.
4. The device of claim 3 , wherein the dielectric liner contacts a gate stack of the first transistor.
5. The device of claim 1 further comprising an insulating spacer on a sidewall of the metal contact.
6. The device of claim 5 , wherein the insulating spacer contacts the semiconductor material.
7. The device of claim 5 further comprising a void between the insulating spacer and the semiconductor material.
8. The device of claim 5 further comprising an insulating material between the insulating spacer and the semiconductor material.
9. A device comprising:
a device layer comprising a plurality of transistors;
a front-side interconnect structure on a front-side of the device layer; and
a backside interconnect structure on a backside of the device layer, the backside interconnect structure comprising:
a semiconductor material on the backside of the device layer;
a first insulating material on the backside of the device layer, wherein the first insulating material contacts a gate stack in the device layer, and wherein the semiconductor material separates the first insulating material from a corner region of a first source/drain region in the device layer;
a contact extending through the first insulating material to a second source/drain region in the device layer; and
a conductive line electrically connected to the second source/drain region by the contact.
10. The device of claim 9 , wherein the semiconductor material has a surface in a <111> crystalline plane.
11. The device of claim 9 further comprising a void between the contact and the first insulating material.
12. The device of claim 9 further comprising a second insulating material between the contact and the first insulating material.
13. The device of claim 9 further comprising an insulating spacer on sidewalls of the contact, the insulating spacer separates the contact from the first insulating material.
14. The device of claim 13 further comprising an epitaxial material between the first source/drain region and the first insulating material, wherein the semiconductor material is disposed on a sidewall of the epitaxial material.
15. A method comprising:
forming a device layer on a semiconductor substrate, the device layer comprising a plurality of transistors, wherein forming the device layer comprises:
etching a first recess and a second recess in the semiconductor substrate;
epitaxially growing a first semiconductor material in the first recess;
epitaxially growing a second semiconductor material over the first semiconductor material in the first recess; and
epitaxially growing a third semiconductor material in the second recess;
forming a first interconnect structure over a backside of the device layer, wherein forming the first interconnect structure comprises:
removing a portion of semiconductor substrate to expose the first semiconductor material;
depositing a first dielectric layer over remaining portions of the semiconductor substrate and around the first semiconductor material;
removing the first semiconductor material to define a third recess, wherein the remaining portions of the semiconductor substrate masks at least a corner region of the third semiconductor material while removing the first semiconductor material, and wherein the third recess exposes the second semiconductor material; and
forming a contact in the second recess and electrically connected to the second semiconductor material.
16. The method of claim 15 , wherein removing the portion of the semiconductor substrate further exposes a gate stack of the device layer.
17. The method of claim 16 , wherein forming the device layer further comprises:
epitaxially growing a fourth semiconductor material in the second recess, wherein the third semiconductor material is over the fourth semiconductor material, and wherein the remaining portions of the semiconductor substrate contacts a sidewall of the fourth semiconductor material.
18. The method of claim 17 further comprising removing the semiconductor substrate from the third recess before forming the contact.
19. The method of claim 17 further comprising oxidizing the semiconductor substrate in the third recess to form an insulating material.
20. The method of claim 17 further comprising replacing the semiconductor substrate in the third recess with an insulating material.