IP Library › Granted Patent US 11,538,385

Granted Patent B2

US 11,538,385 · App. 17/355,858 · Granted Dec 27, 2022

Gate driving unit, gate driving circuit, gate driving method and display device

Inventors: Zhichong Wang (Beijing, CN); Guangcai Yuan (Beijing, CN); Fuqiang Li (Beijing, CN); Jing Feng (Beijing, CN); Xinglong Luan (Beijing, CN); Peng Liu (Beijing, CN)

Assignee: BOE TECHNOLOGY GROUP CO., LTD.

G09G3/20 G06F3/0412 G06F3/0416 G09G3/3266 G09G3/3677 G09G2300/0426 G09G2300/0819 G09G2310/0267 G09G2310/08 G09G2320/0204 G09G2330/02

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Quick Facts

Patent No.: US 11,538,385
App. No.: 17/355,858
Granted: Dec 27, 2022
Kind: B2

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Abstract

A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.

Claims (97)

1. A gate driving unit, comprising:

a pull-up node denoising circuit;

a pull-down node control circuit;

a pull-up node control circuit; and

an energy storage circuit;

wherein the pull-up node denoising circuit is electrically coupled to an input terminal, a pull-down node and a first pull-up node, respectively; the pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or decoupling between the first pull-up node and the input terminal;

wherein the pull-down node control circuit is electrically coupled to a second pull-up node, the pull-down node and the input terminal, respectively; the pull-down node control circuit is configured to, under control of a control voltage provided by a control voltage terminal, control the potential of the pull-down node; and under control of a potential of the second pull-up node, control coupling or decoupling between the pull-down node and the input terminal;

wherein the pull-up node control circuit is electrically coupled to an anti-leakage control terminal, the first pull-up node and the second pull-up node, respectively; the pull-up node control circuit is configured to, under control of an anti-leakage control voltage provided by the anti-leakage control terminal, control coupling or decoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node;

wherein the energy storage circuit is electrically coupled to the second pull-up node and is configured to store electric energy,

wherein the pull-down node includes a first pull-down node and a second pull-down node; and the pull-up node denoising circuit includes a first pull-up node denoising transistor and a second pull-up node denoising transistor; a control electrode of the first pull-up node denoising transistor is electrically coupled to the first pull-down node; a first electrode of the first pull-up node denoising transistor is electrically coupled to the pull-up node; a second electrode of the first pull-up node denoising transistor is electrically coupled to the input terminal; a control electrode of the second pull-up node denoising transistor is electrically coupled to the second pull-down node; a first electrode of the second pull-up node denoising transistor is electrically coupled to the pull-up node; and a second electrode of the second pull-up node denoising transistor is electrically coupled to the input terminal.

2. The gate driving unit according to claim 1 , wherein the pull-up node denoising circuit is electrically coupled to one pull-down node; the pull-up node denoising circuit includes a pull-up node denoising transistor; a control electrode of the pull-up node denoising transistor is electrically coupled to the pull-down node; a first electrode of the pull-up node denoising transistor is electrically coupled to the pull-up node; and a second electrode of the pull-up node denoising transistor is electrically coupled to the input terminal.

3. The gate driving unit according to claim 1 , wherein the anti-leakage control terminal is the pull-down node;

the gate driving unit further includes a first pull-up node reset circuit;

the first pull-up node reset circuit is electrically coupled to a reset terminal, the second pull-up node and a reset voltage terminal, respectively; the first pull-up node reset circuit is configured to, under control of a reset signal provided by the reset terminal, control coupling or decoupling between the second pull-up node and the reset voltage terminal.

4. The gate driving unit according to claim 3 , wherein the first pull-up node reset circuit includes a first pull-up node reset transistor;

a gate electrode of the first pull-up node reset transistor is electrically coupled to the reset terminal; a drain electrode of the first pull-up node reset transistor is electrically coupled to the second pull-up node; a source electrode of the first pull-up node reset transistor is electrically coupled to the reset voltage terminal.

5. The gate driving unit according to claim 1 , wherein the anti-leakage control terminal is the control voltage terminal or the pull-down node;

the pull-up node control circuit includes a pull-up control transistor, and the energy storage circuit includes a storage capacitor;

a gate electrode of the pull-up control transistor is electrically coupled to the control voltage terminal or the pull-down node; a first electrode of the pull-up control transistor is electrically coupled to the second pull-up node; a second electrode of the pull-up control transistor is electrically coupled to the first pull-up node;

a first terminal of the storage capacitor is electrically coupled to the second pull-up node; a second terminal of the storage capacitor is electrically coupled to a gate driving signal output terminal.

6. The gate driving unit according to claim 1 , wherein the control voltage terminal includes a first control voltage terminal and a second control voltage terminal;

the pull-down node control circuit is configured to, under control of a first control voltage provided by the first control voltage terminal, control a potential of the first pull-down node; under control of the second pull-up node, control coupling or decoupling between the first pull-down node and the input terminal; under control of a second control voltage provided by the second control voltage terminal, control a potential of the second pull-down node; and under control of the second pull-up node, control the first pull-down node to be electrically coupled to the input terminal.

7. The gate driving unit according to claim 6 , wherein the pull-up node control circuit includes a first pull-up control transistor and a second pull-up control transistor; the energy storage circuit includes a storage capacitor;

a control electrode of the first pull-up control transistor is electrically coupled to the first pull-down node; a first electrode of the first pull-up control transistor is electrically coupled to the second pull-up node; a second electrode of the first pull-up control transistor is electrically coupled to the first pull-up node;

a control electrode of the second pull-up control transistor is electrically coupled to the second pull-down node; a first electrode of the second pull-up control transistor is electrically coupled to the second pull-up node; a second electrode of the second pull-up control transistor is electrically coupled to the first pull-up node;

a first terminal of the storage capacitor is electrically coupled to the second pull-up node; and a second terminal of the storage capacitor is electrically coupled to a gate driving signal output terminal.

8. The gate driving unit according to claim 6 , wherein the pull-up node control circuit includes a first pull-up control transistor and a second pull-up control transistor; the energy storage circuit includes a storage capacitor;

a control electrode of the first pull-up control transistor is electrically coupled to the first control voltage terminal; a first electrode of the first pull-up control transistor is electrically coupled to the second pull-up node; a second electrode of the first pull-up control transistor is electrically coupled to the first pull-up node;

a control electrode of the second pull-up control transistor is electrically coupled to the second control voltage terminal; a first electrode of the second pull-up control transistor is electrically coupled to the second pull-up node; a second electrode of the second pull-up control transistor is electrically coupled to the first pull-up node;

a first terminal of the storage capacitor is electrically coupled to the second pull-up node; and a second terminal of the storage capacitor is electrically coupled to the gate driving signal output terminal.

9. The gate driving unit according to claim 6 , wherein the pull-down node control circuit includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor;

a control electrode of the fifth pull-down control transistor and a first electrode of the fifth pull-down control transistor are both electrically coupled to the first control voltage terminal;

a control electrode of the first pull-down control transistor is electrically coupled to a second electrode of the fifth pull-down control transistor; a first electrode of the first pull-down control transistor is electrically coupled to the first control voltage terminal; a second electrode of the first pull-down control transistor is electrically coupled to the first pull-down node;

a control electrode of the sixth pull-down control transistor is electrically coupled to the second pull-up node; a first electrode of the sixth pull-down control transistor is electrically coupled to the second electrode of the fifth pull-down control transistor; a second electrode of the sixth pull-down control transistor is electrically coupled to the input terminal;

a control electrode of the second pull-down control transistor is electrically coupled to the second pull-up node; a first electrode of the second pull-down control transistor is electrically coupled to the first pull-down node; a second electrode of the second pull-down control transistor is electrically coupled to the input terminal;

a control electrode of the seventh pull-down control transistor and a first electrode of the seventh pull-down control transistor are both electrically coupled to the second control voltage terminal;

a control electrode of the third pull-down control transistor and a first electrode of the third pull-down control transistor are both electrically coupled to a second electrode of the seventh pull-down control transistor; a second electrode of the third pull-down control transistor is electrically coupled to the second pull-down node;

a control electrode of the eighth pull-down control transistor is electrically coupled to the second pull-up node; a first electrode of the eighth pull-down control transistor is electrically coupled to the second electrode of the seventh pull-down control transistor; a second electrode of the eight pull-down control transistor is electrically coupled to the input terminal;

a control electrode of the fourth pull-down control transistor is electrically coupled to the second pull-up node; a first electrode of the fourth pull-down control transistor is electrically coupled to the second pull-down node; a second electrode of the fourth pull-down control transistor is electrically coupled to the input terminal.

10. The gate driving unit according to claim 1 , wherein the gate driving unit further includes a second pull-up node reset circuit;

the second pull-up node reset circuit is electrically coupled to the first pull-up node, and is configured to reset the potential of the first pull-up node in a reset phase.

11. The gate driving unit according to claim 10 , wherein the second pull-up node reset circuit includes a second pull-up node reset transistor;

a control electrode of the second pull-up node reset transistor is electrically coupled to a first clock signal terminal; a first electrode of the second pull-up node reset transistor is electrically coupled to the first pull-up node; a second electrode of the second pull-up node reset transistor is electrically coupled to the input terminal; or,

a control electrode of the second pull-up node reset transistor is electrically coupled to a reset terminal; a first electrode of the second pull-up node reset transistor is electrically coupled to the first pull-up node; a second electrode of the second pull-up node reset transistor is electrically coupled to the input terminal or a first low-voltage terminal.

12. The gate driving unit according to claim 1 , wherein the gate driving unit further includes a third pull-up node reset circuit;

the third pull-up node reset circuit is electrically coupled to an inter-frame reset terminal, the first pull-up node and a first low-voltage terminal, respectively; the third pull-up node reset circuit is configured to, under control of an inter-frame reset signal provided by the inter-frame reset terminal, control coupling or decoupling between the first pull-up node and the first low-voltage terminal during an inter-frame blank period.

13. The gate driving unit according to claim 12 , wherein the third pull-up node reset circuit includes a third pull-up node reset transistor;

a gate electrode of the third pull-up node reset transistor is electrically coupled to an inter-frame reset terminal; a drain electrode of the third pull-up node reset transistor is electrically coupled to the first pull-up node; a source electrode of the third pull-up node reset transistor is electrically coupled to the first low-voltage terminal.

14. The gate driving unit according to claim 1 , wherein the gate driving unit further includes a carry-signal output circuit and a gate driving signal output circuit;

the carry-signal output circuit is electrically coupled to the second pull-up node, a clock signal terminal, the pull-down node, a carry-signal output terminal and a first low-voltage terminal, respectively; the carry-signal output circuit is configured to, under control of the potential of the second pull-up node, control the carry-signal output terminal to be electrically coupled to the clock signal terminal, and, under control of the potential of the pull-down node, control coupling or decoupling between the carry-signal output terminal and the first low-voltage terminal;

the gate driving signal output circuit is electrically coupled to the second pull-up node, the clock signal terminal, the pull-down node, the gate driving signal output terminal, and a second low-voltage terminal, respectively; the gate driving signal output circuit is configured to, under control of the potential of the second pull-up node, control the gate driving signal output terminal to be electrically coupled to the clock signal terminal, and, under control of the potential of the pull-down node, control coupling or decoupling between the gate driving signal output terminal and the second low-voltage terminal;

a first low-voltage provided by the first low-voltage terminal is less than a second low-voltage provided by the second low-voltage terminal.

15. The gate driving unit according to claim 14 , wherein the carry-signal output circuit includes a first carry-signal output transistor, a second carry-signal output transistor, and a third carry-signal output transistor; the gate driving signal output circuit includes a first gate driving output transistor, a second gate driving output transistor and a third gate driving output transistor; the pull-down node includes a first pull-down node and a second pull-down node;

a gate electrode of the first carry-signal output transistor is electrically coupled to the second pull-up node; a drain electrode of the first carry-signal output transistor is electrically coupled to the clock signal terminal; a source electrode of the first carry-signal output transistor is electrically coupled to the carry-signal output terminal; the clock signal terminal is configured to provide a clock signal;

a gate electrode of the second carry-signal output transistor is electrically coupled to the first pull-down node; a drain electrode of the second carry-signal output transistor is electrically coupled to the carry-signal output terminal; a source electrode of the second carry-signal output transistor is electrically coupled to the first low-voltage terminal; the first low-voltage terminal is configured to provide a first low-voltage;

a gate electrode of the third carry-signal output transistor is electrically coupled to the second pull-down node; a drain electrode of the third carry-signal output transistor is electrically coupled to the carry-signal output terminal; a drain electrode of the third carry-signal output transistor is electrically coupled to the first low-voltage terminal;

a gate electrode of the first gate driving output transistor is electrically coupled to the second pull-up node; a drain electrode of the first gate driving output transistor is electrically coupled to the clock signal terminal; a source electrode of the first gate driving output transistor is electrically coupled to the gate driving signal output terminal;

a gate electrode of the second gate driving output transistor is electrically coupled to the first pull-down node; a drain electrode of the second gate driving output transistor is electrically coupled to the gate driving signal output terminal; a source electrode of the second gate driving output transistor is electrically coupled to the second low-voltage terminal; the second low-voltage terminal is configured to provide a second low-voltage;

a gate electrode of the third gate driving output transistor is electrically coupled to the second pull-down node; a drain electrode of the third gate driving output transistor is electrically coupled to the gate driving signal output terminal; a source electrode of the third gate driving output transistor is electrically coupled to the first low-voltage terminal.

16. A gate driving method applied to the gate driving unit according to claim 1 , comprising:

under control of a potential of the pull-down node, controlling, by the pull-up node denoising circuit, coupling or decoupling between the first pull-up node and the input terminal;

under control of a control voltage provided by the control voltage terminal, controlling, by the pull-down node control circuit, coupling or decoupling between the control voltage terminal and the pull-down node; and, under control of a potential of the second pull-up node, controlling, by the pull-down node control circuit, coupling or decoupling between the pull-down node and the input terminal;

under control of an anti-leakage control voltage provided by the anti-leakage control terminal, controlling, by the pull-up node control circuit, coupling or decoupling between the first pull-up node and the second pull-up node, and maintaining the potential of the second pull-up node.

17. A gate driving circuit, comprising:

multiple stages of gate driving units;

wherein each gate driving unit includes:

a pull-up node denoising circuit;

a pull-down node control circuit;

a pull-up node control circuit; and

an energy storage circuit;

wherein the energy storage circuit is electrically coupled to the second pull-up node and is configured to store electric energy,

18. The gate driving circuit according to claim 17 , wherein each gate driving unit further includes a carry-signal output circuit and a gate driving signal output circuit;

a first low-voltage provided by the first low-voltage terminal is less than a second low-voltage provided by the second low-voltage terminal;

wherein the input terminal of each gate driving unit is electrically coupled to the carry-signal output terminal of an adjacent upper-level gate driving unit.

19. A display device, comprising:

a gate driving circuit including multiple stages of gate driving units;

wherein each gate driving unit includes:

a pull-up node denoising circuit;

a pull-down node control circuit;

a pull-up node control circuit; and

an energy storage circuit;

wherein the energy storage circuit is electrically coupled to the second pull-up node and is configured to store electric energy;

wherein each gate driving unit further includes a carry-signal output circuit and a gate driving signal output circuit;

a first low-voltage provided by the first low-voltage terminal is less than a second low-voltage provided by the second low-voltage terminal;

wherein the input terminal of each gate driving unit is electrically coupled to the carry-signal output terminal of an adjacent upper-level gate driving unit,

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2021

From: WANG, ZHICHONG; YUAN, GUANGCAI; LI, FUQIANG; FENG, JING; LUAN, XINGLONG; LIU, PENG

To: BOE TECHNOLOGY GROUP CO., LTD.,

Reel/Frame 056718/0509 →

Priority Claims (1)

CN 202011163133.2 · Oct 27, 2020 · national

Continuity (1)

Related Publication 20220130309A1 · Apr 28, 2022