Systems and methods for generating a controllable-width pulse signal
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
1. A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages;
a replica delay line having stages substantially similar to the delay line;
a delay per stage calculation circuit configured to determine a per-stage delay of the delay line using a first clock input and a sampling clock input;
a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay;
wherein the delay line receives a second clock input;
wherein the delay per stage calculation circuit determines the per-stage delay of the delay line based on operation of the replica delay line receiving the first clock input.
2. The circuit of claim 1 , wherein the delay per stage calculation circuit comprises:
a time to digital converter configured to sample an output of the replica delay line according to the sampling clock input.
3. The circuit of claim 2 , wherein the delay per stage calculation circuit comprises:
a period stage calculator configured use the sampled output of the replica delay line to determine a number of sampling clock periods are in a cycle of the sampled output of the replica delay line.
4. The circuit of claim 3 , wherein the per-stage delay is determined based on the determined number of sampling clock periods and the frequency of the first clock input.
5. The circuit of claim 1 , wherein the second clock input having a lower frequency than the first clock input.
6. The circuit of claim 1 , wherein the second clock input has a lower frequency than both the first clock input and the sampling clock input.
7. The circuit of claim 1 , wherein the first clock input operates at a frequency of 4 to 5 GHz.
8. The circuit of claim 1 , wherein the first clock input operates at a frequency 10 to 100 times faster than the second clock input.
9. A method of generating a pulse output having a controllable pulse width, comprising:
accessing a delay line having a plurality of stages;
providing a first clock input to a replica delay line having stages substantially similar to the delay line,
sampling an output of the replica delay line using a sampling clock input,
determining a per-stage delay of the delay line based on operation of the replica delay line; and
generating the pulse output using the delay line based on the per-stage delay by providing the delay line a second clock input.
10. The method of claim 9 , further comprising:
determining a number of sampling clock periods are in a cycle of the sampled output of the replica delay line.
11. The method of claim 10 , wherein the per-stage delay is determined based on the determined number of sampling clock periods and a frequency of the first clock input.
12. The method of claim 9 , wherein the second clock input has a lower frequency than both the first clock input and the sampling clock input.
13. The method of claim 9 , wherein the output of the replica delay line is sampled by a time-to-digital converter.
14. The method of claim 13 , wherein a period stage calculator processes the samples from the time-to-digital converter to determine a per-stage delay indication measurement.
15. The method of claim 14 , wherein the per-stage delay of the delay line is determined from the per-stage delay indication measurement.
16. A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages;
a delay per stage calculation circuit configured to determine a per-stage delay of the delay line using a sampling clock input;
a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay;
wherein the delay line receives a fast clock input;
wherein the delay per stage calculation circuit determines the per-stage delay of the delay line based on operation of the delay line receiving the fast clock input;
wherein the delay per stage calculation circuit comprises: a time-to-digital converter configured to sample an output of the delay line according to the sampling clock input; and a period stage calculator configured use the sampled output of the delay line to determine a number of sampling clock periods are in a cycle of the sampled output of the delay line.
17. The circuit of claim 16 , wherein the pulse generation circuit selectively accesses outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
18. The circuit of claim 17 , further comprising an SR flip flop that receives the outputs of the two stages and generates the pulse output.
19. The circuit of claim 17 , wherein the two stages are selected based on a selected pulse output width and the per-stage delay.
20. The circuit of claim 16 , wherein the fast clock input has a frequency of 4 to 5 GHz.