IP Library Granted Patent US 11,550,592
Granted Patent B2
US 11,550,592 · App. 16/024,047 · Granted Jan 10, 2023

Methods and apparatus to utilize non-volatile memory for computer system boot

Inventors: Karunakara Kotary (Portland, OR); Sean Dardis (Hillsboro, OR); Michael Kubacki (Hillsboro, OR); Ankit Sinha (Hillsboro, OR)
Assignee: Intel Corporation
G06F9/4401G06F3/061G06F3/0629G06F3/0644G06F3/0679G06F9/44505G06F12/0246G06F12/0638G06F12/0646G06F12/0868G06F2212/1024G06F2212/206G06F2212/225G06F2212/401G06F2212/7206
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Quick Facts
Patent No.
US 11,550,592
App. No.
16/024,047
Granted
Jan 10, 2023
Kind
B2
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to utilize non-volatile memory for computer system boot. An example processor platform includes a non-volatile memory coupled to a processing unit via a bus, and a microcontroller to: configure the processing unit to store, on the non-volatile memory, a heap and a stack for execution of boot code, and configure the processing unit to execute the boot code stored on the non-volatile memory.

Claims (37)

1. A processor platform comprising:

a non-volatile memory coupled to a processing unit via a bus; and

a logic circuit to:

copy boot code and host firmware data to the non-volatile memory during a first boot process;

determine, during a subsequent boot process and prior to initialization of the processing unit, whether the host firmware data for the processor platform is provisioned on the non-volatile memory or another memory; and

in response to a determination that the host firmware data is provisioned on the non-volatile memory, map a reset vector of the processing unit to the non-volatile memory to configure the processing unit to execute the boot code stored on the non-volatile memory the with a heap and a stack stored on the non-volatile memory.

2. A processor platform as defined in claim 1 , wherein the non-volatile memory stores files of an operating system installed on the processor platform.

3. A processor platform as defined in claim 1 , wherein the non-volatile memory is two level memory that is capable of operating as volatile memory and non-volatile memory.

4. A processor platform as defined in claim 1 , wherein the logic circuit is to transfer at least one of the boot code and boot data from a storage device to the non-volatile memory.

5. A processor platform as defined in claim 4 , wherein the logic circuit is further to decompress at least one of the boot code and the boot data from the storage device before transferring the decompressed at least one of the boot code and the boot data to the non-volatile memory.

6. A processor platform as defined in claim 4 , wherein the storage device is a flash storage device coupled to the processing unit via a platform controller.

7. A processor platform as defined in claim 1 , wherein the processing unit includes a far memory controller coupled to the non-volatile memory to communicate with the non-volatile memory.

8. A processor platform as defined in claim 1 , wherein the logic circuit is to:

configure the processing unit to store, on the non-volatile memory, the heap and the stack for execution of the boot code, wherein the non-volatile memory includes a first partition to store files of an operating system installed on the processor platform, a second partition to store the boot code, and a third partition to store host firmware data; and

configure the processing unit to begin the first boot process using boot code stored on a storage device to initialize main memory.

9. A non-transitory computer readable medium comprising instructions that, when executed, cause a machine to:

copy boot code and host firmware data to a non-volatile memory during a first boot process;

determine, during a subsequent boot process and prior to initialization of a processing unit, whether the host firmware data for a processor platform is provisioned on the non-volatile memory or another memory; and

in response to a determination that the host firmware data is provisioned on the non-volatile memory, map a reset vector of the processing unit to the non-volatile memory to configure the processing unit to execute the boot code stored on the non-volatile memory with a heap and a stack stored on the non-volatile memory.

10. A non-transitory computer readable medium as defined in claim 9 , wherein the non-volatile memory stores files of an operating system.

11. A non-transitory computer readable medium as defined in claim 9 , wherein the non-volatile memory is two level memory that is capable of operating as volatile memory and non-volatile memory.

12. A non-transitory computer readable medium as defined in claim 9 , wherein the instructions, when executed, cause the machine to transfer at least one of the boot code and boot data from a storage device to the non-volatile memory.

13. A non-transitory computer readable medium as defined in claim 12 , wherein the instructions, when executed, cause the machine to decompress at least one of the boot code and the boot data from the storage device before transferring the decompressed at least one of the boot code and the boot data to the non-volatile memory.

14. A non-transitory computer readable medium as defined in claim 12 , wherein the storage device is a flash storage device coupled to the processing unit via a platform controller.

15. A non-transitory computer readable medium as defined in claim 9 , wherein the processing unit includes a far memory controller coupled to the non-volatile memory to communicate with the non-volatile memory.

16. A non-transitory computer readable medium as defined in claim 9 , wherein the instructions, when executed, cause the machine to:

configure the processing unit to store, on the non-volatile memory, the heap and the stack for execution of the boot code, wherein the non-volatile memory includes a first partition to store files of an operating system installed on the processor platform, a second partition to store the boot code, and a third partition to store host firmware data; and

configure the processing unit to begin the first boot process using boot code stored on a storage device to initialize main memory.

17. A method comprising:

copying boot code and host firmware data to a non-volatile memory during a first boot process;

determining, during a boot process subsequent to the first boot process and prior to initialization of a processing unit, the host firmware data for a processor platform is provisioned on the non-volatile memory; and

mapping a reset vector of the processing unit to the non-volatile memory to configure the processing unit to execute the boot code stored on the non-volatile memory with a heap and a stack stored on the non-volatile memory.

18. A method as defined in claim 17 , wherein the non-volatile memory stores files of an operating system.

19. A method as defined in claim 17 , wherein the non-volatile memory is two level memory that is capable of operating as volatile memory and non-volatile memory.

20. A method as defined in claim 17 , further comprising:

configuring the processing unit to store, on the non-volatile memory, the heap and the stack for execution of the boot code, wherein the non-volatile memory includes a first partition to store files of an operating system installed on the processor platform, a second partition to store the boot code, and a third partition to store host firmware data; and

configuring the processing unit to begin the first boot process using boot code stored on a storage device to initialize main memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2018
From: KOTARY, KARUNAKARA; DARDIS, SEAN; KUBACKI, MICHAEL; SINHA, ANKIT
To: INTEL CORPORATION
Reel/Frame 046610/0658 →
Continuity (1)
Related Publication 20190042272A1 · Feb 7, 2019