Semiconductor integrated circuit and receiver device
A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.
1. A semiconductor integrated circuit, comprising:
a converter configured to convert an analog signal into a digital signal based on a clock signal;
a comparator circuit configured to determine values of data based on the digital signal;
a recovery circuit configured to recover the clock signal based on the digital signal and the data; and
a control circuit configured to control the recovery circuit,
wherein
the recovery circuit includes:
a phase detector configured to calculate a sum of a first value and a first offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and
a loop filter configured to calculate a correction amount of the phase of the clock signal based on the sum, and
the control circuit is configured to gradually change the first offset from a second value to zero after the second value is added as the first offset.
2. The semiconductor integrated circuit according to claim 1 , wherein
the digital signal includes a third value corresponding to a first sampling time and a fourth value corresponding to a second sampling time,
the data includes a fifth value corresponding to the third value and a sixth value corresponding to the fourth value, and
the phase detector is further configured to calculate the first value based on a difference between a product of the third value and the sixth value and a product of the fourth value and the fifth value.
3. The semiconductor integrated circuit according to claim 1 , wherein
the first offset is negative or positive, and
an absolute value of the second value is equal to or greater than a maximum value of an absolute value of the first value.
4. The semiconductor integrated circuit according to claim 1 , wherein the phase detector is an MM baud-rate phase detector.
5. The semiconductor integrated circuit according to claim 1 , wherein the control circuit is configured to maintain a value of the first offset to the second value in a period longer than a cycle in which the clock signal is recovered.
6. The semiconductor integrated circuit according to claim 1 , wherein the loop filter includes an integrator to which an input value based on the sum is input and from which an output value limited to within a first range is output.
7. The semiconductor integrated circuit according to claim 6 , wherein
the control circuit is configured to:
store the output value as a second offset in a state where the first offset is not given,
after storing the second offset, reset the output value and change a range in which the output value is clipped to a second range, the second range being narrower than the first range, and
add the second offset to the output value in a state where the first offset is given.
8. The semiconductor integrated circuit according to claim 1 , wherein the data includes data having 2 bits per symbol.
9. A receiver device, comprising:
a semiconductor integrated circuit; and
a data processing circuit configured to utilize data output from the semiconductor integrated circuit,
wherein
the semiconductor integrated circuit includes:
a converter configured to convert an analog signal into a digital signal based on a clock signal;
a comparator circuit configured to determine values of data based on the digital signal;
a recovery circuit configured to recover the clock signal based on the digital signal and the data; and
a control circuit configured to control the recovery circuit,
and wherein
the recovery circuit includes:
a phase detector configured to calculate a sum of a first value and a first offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and
a loop filter configured to calculate a correction amount of the phase of the clock signal based on the sum, and
the control circuit is configured to gradually change the first offset from a second value to zero after the second value is added as the first offset.
10. The receiver device according to claim 9 , wherein
the digital signal includes a third value corresponding to a first sampling time and a fourth value corresponding to a second sampling time,
the data includes a fifth value corresponding to the third value and a sixth value corresponding to the fourth value, and
the phase detector is further configured to calculate the first value based on a difference between a product of the third value and the sixth value and a product of the fourth value and the fifth value.
11. The receiver device according to claim 9 , wherein
the first offset is negative or positive, and
an absolute value of the second value is equal to or greater than a maximum value of an absolute value of the first value.
12. The receiver device according to claim 9 , wherein the phase detector is an MM baud-rate phase detector.
13. The receiver device according to claim 9 , wherein the control circuit is configured to maintain a value of the first offset to the second value in a period longer than a cycle in which the clock signal is recovered.
14. The receiver device according to claim 9 , wherein the loop filter includes an integrator to which an input value based on the sum is input and from which an output value limited to within a first range is output.
15. The receiver device according to claim 14 , wherein
the control circuit is configured to:
store the output value as a second offset in a state where the first offset is not given,
after storing the second offset, reset the output value and change a range in which the output value is clipped to a second range, the second range being narrower than the first range, and
add the second offset to the output value in a state where the first offset is given.
16. The receiver device according to claim 9 , wherein the data includes data having 2 bits per symbol.