Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.
1. A method of forming an integrated structure, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack of alternating first and second levels;
recessing the first levels relative to the second levels; the second levels having terminal ends extending beyond the recessed first levels; the terminal ends having surfaces of the second material; the recessed first levels having surfaces of the first material; the surfaces of the first and second materials forming a first undulating sidewall surface of the opening;
forming dielectric material along the undulating sidewall surface;
the dielectric material wrapping around the terminal ends; the dielectric material having first portions along the surfaces of the first material, and having second portions along the surfaces of the second material; an outer surface of the dielectric material being a second undulating sidewall surface of the opening;
forming third material adjacent the dielectric material and along the second undulating sidewall surface; an outer surface of the third material being a third undulating sidewall surface of the opening; the third undulating sidewall surface having peak regions along the second levels, and having cavities along the first levels;
forming a fourth material within the cavities;
selectively forming charge-storage material along the third material relative to the fourth material to form segments of the charge-storage material along the peak regions, such segments being vertically spaced from one another by gaps adjacent to the fourth material;
forming tunneling material adjacent the charge-storage material;
forming channel material adjacent the tunneling material;
removing the second material to leave voids;
oxidizing the third material with oxidant flowed into the voids, the oxidation forming charge-blocking material from the third material; and
forming conductive levels within the voids; the conductive levels having terminal regions adjacent the dielectric material, and having nonterminal regions proximate the terminal regions; the dielectric material being adjacent to the terminal regions and not being adjacent to the nonterminal regions.
2. The method of claim 1 wherein the third material comprises silicon nitride, and wherein the charge-blocking material comprises silicon oxynitride.
3. The method of claim 1 wherein the third material comprises silicon, and wherein the charge-blocking material comprises silicon dioxide.
4. The method of claim 1 wherein the dielectric material comprises silicon dioxide.
5. The method of claim 1 wherein the dielectric material is a high-k dielectric material.
6. The method of claim 5 further comprising removing segments of the high-k dielectric material from ends of the voids prior to flowing the oxidant into the voids.
7. The method of claim 5 wherein the high-k dielectric material is a first high-k dielectric material, and further comprising forming a second high-k dielectric material within the voids to line the voids prior to forming the conductive levels within the voids.
8. The method of claim 7 wherein the first and second high-k dielectric materials are a same composition as one another.
9. The method of claim 7 wherein the first and second high-k dielectric materials are different compositions relative to one another.
10. The method of claim 1 further comprising replacing at least some of the first material with second voids along the first levels.
11. The method of claim 1 wherein each of the segments has a substantially flat configuration.
12. The method of claim 1 wherein the fourth material comprises silicon dioxide.