Semiconductor device with stacked terminals
A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.
1. A semiconductor device comprising:
a housing;
a substrate inside the housing;
a first semiconductor circuit disposed on the substrate;
a second semiconductor circuit disposed on the substrate, wherein the first semiconductor circuit and the second semiconductor circuit each have a top side and a bottom side;
a first planar terminal comprising:
a first portion of the first planar terminal electrically connected to the top side of the first semiconductor circuit, and a second portion of the first planar terminal extending away from the housing, the first portion of the first planar terminal and the second portion of the first planar terminal being part of a single piece conductive sheet; and
a second planar terminal comprising:
a first portion of the second planar terminal electrically connected to the top side of the second semiconductor circuit, a second portion of the second planar terminal extending away from the housing, and a third step shaped portion of the second planar terminal positioned between the first portion of the second planar terminal and the second portion of the second planar terminal, wherein at least the second portion of the first planar terminal and at least the second portion of the second planar terminal are stacked in a direction that is normal to the substrate such that the second planar terminal overlays on top of the first planar terminal inside the housing, and wherein the second portion of the first planar terminal and the first portion of the second planar terminal are coplanar.
2. The semiconductor device of claim 1 , wherein the first semiconductor circuit and the second semiconductor circuit are positioned in a common plane on top of the substrate, wherein the first portion of the first planar terminal abuts the first semiconductor circuit, and wherein the first portion of the second planar terminal is parallel to and offset from the second portion of the second planar terminal thereof by the third step shaped portion of the second planar terminal, and wherein the first portion of the second planar terminal abuts the second semiconductor circuit.
3. The semiconductor device of claim 2 , wherein the housing has a common opening through which the second portion of the first planar terminal and the second portion of the second planar terminal extend away from the housing in a stacked configuration.
4. The semiconductor device of claim 2 , further comprising an electrical insulation layer disposed between the first planar terminal and the second planar terminal.
5. The semiconductor device of claim 1 , wherein the first and second semiconductor circuits are positioned in a common plane on top of the substrate, the semiconductor device further comprising:
a first busbar abutting the first semiconductor circuit, wherein the first planar terminal abuts the first busbar; and
a second busbar abutting the second semiconductor circuit, wherein the second planar terminal abuts the second busbar.
6. The semiconductor device of claim 5 , wherein the first busbar is planar and extends out through the housing, and wherein the first planar terminal abuts the first busbar outside the housing.
7. The semiconductor device of claim 5 , wherein the second busbar is planar and has a portion thereof exposed through an opening in the housing.
8. The semiconductor device of claim 7 , wherein the second planar terminal is positioned on an opposite side of the first planar terminal from the first and second busbars, wherein the second planar terminal contains a contact portion offset from a main portion thereof by an offsetting portion, and wherein the contact portion abuts the portion of the second busbar.
9. The semiconductor device of claim 1 , wherein the first planar terminal and the second planar terminal are overlaying for most of their respective surface areas.
10. The semiconductor device of claim 1 , wherein the first planar terminal and the second planar terminal has a width that is at least 70% of a width of the semiconductor device.
11. The semiconductor device of claim 1 , wherein the first planar terminal is a positive terminal, and wherein the second planar terminal is a negative terminal.
12. The semiconductor device of claim 1 , wherein the first semiconductor circuit and the second semiconductor circuit comprise silicon.
13. The semiconductor device of claim 1 , wherein the third step shaped portion is formed by stamping or bending.
14. The semiconductor device of claim 1 , wherein the substrate comprises a ceramic layer and is configured to direct heat away from the semiconductor device and electrically insulate at least one or more high-voltage semiconductor circuits of the semiconductor device.
15. The semiconductor device of claim 1 , wherein the first portion of the first planar terminal is directly electrically connected to the top side of the first semiconductor circuit, and wherein the first portion of the second planar terminal is directly electrically connected to the top side of the second semiconductor circuit.
16. The semiconductor device of claim 1 , wherein the second portion of the first planar terminal and the second portion of the second planar terminal both extend away from the housing on the same side of the housing in a stacked configuration.
17. The semiconductor device of claim 1 , wherein at least the second portion of the first planar terminal is situated on one horizontal plane and at least the second portion of the second planar terminal is situated on another horizontal plane.
18. The semiconductor device of claim 1 , wherein the at least second portion of the second planar terminal overlays on top of the at least second portion of the first planar terminal with only an electrical insulation layer directly between the at least second portion of the first planar terminal and the at least second portion of the second planar terminal, and wherein the at least second portion of the second planar terminal and the at least second portion of the first planar terminal are uncovered with laminate material.
19. The semiconductor device of claim 1 , wherein each of the first planar terminal and the second planar terminal is a single piece conductive sheet.
20. The semiconductor device of claim 1 , further comprising an additional first semiconductor circuit and an additional second semiconductor circuit, wherein the first portion of the first planar terminal electrically connects to the topside of both first semiconductor circuits, wherein the first portion of the second planar terminal electrically connects to the topside of both second semiconductor circuits, and wherein at least the first portion of the first planar terminal is part of a single piece conductive sheet and at least the first portion of the second planar terminal is part of another single piece conductive sheet.