Data processing engine arrangement in a device
A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.
1. A device, comprising:
a plurality of data processing engines;
wherein each data processing engine includes:
a memory pool having a plurality of memory banks;
a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks;
a memory mapped switch coupled to the memory pool and another memory mapped switch of at least one neighboring data processing engine; and
a stream switch coupled to each of the plurality of cores and to another stream switch of the at least one neighboring data processing engine;
wherein the plurality of data processing engines are configured to provide deterministic performance;
wherein, within each data processing engine, the plurality of cores of the data processing engine are directly coupled by cascade interfaces that serially connect the plurality of cores; and
wherein, within each data processing engine, a selected core of the plurality of cores is directly coupled to a core of at least one neighboring data processing engine.
2. The device of claim 1 , wherein the memory pool comprises:
a crossbar coupled to each of the plurality of memory banks; and
an interface coupled to each core of the plurality of cores and to the crossbar.
3. The device of claim 2 , wherein each data processing engine further comprises:
a direct memory access engine coupled to the memory pool and to the stream switch, wherein the direct memory access engine is configured to provide data from the memory pool to the stream switch and write data from the stream switch to the memory pool.
4. The device of claim 3 , wherein the memory pool further comprises:
a further interface coupled to the crossbar and to the direct memory access engine.
5. The device of claim 1 , wherein each core of the plurality of cores has shared access to the plurality of memory banks.
6. The device of claim 1 , wherein, within each data processing engine, the memory mapped switch is configured to receive configuration data for programming the data processing engine.
7. The device of claim 6 , wherein the stream switch is programmable to establish connections with different ones of the plurality of data processing engines based upon the configuration data.
8. The device of claim 1 , wherein each core of the plurality of cores is programmable to deactivate.