Package with embedded electronic component being encapsulated in a pressureless way

1. A method of manufacturing an electronic package, the method comprising:

dispensing an adhesive in a spatially-restricted manner to a region of a layer structure of a first stack of a component carrier which forms part of the electronic package;

thereafter placing an electronic component in the adhesive on the layer structure of the first stack;

encapsulating the electronic component by an encapsulant in a pressureless way; and

after encapsulating, forming at least one further layer structure at the layer structure of the first stack to thereby form a second stack beneath the encapsulated electronic component,

wherein the at least one further layer structure comprises a surface protection layer structure,

wherein the surface protection layer structure protects an electrically conductive structure of the first stack.

2. The method as set forth in claim 1 , wherein encapsulating the electronic component is accomplished at a temperature being less than 200° C.

3. The method as set forth in claim 1 , wherein encapsulating the electronic component comprises a deposition of encapsulation material by at least one of the following procedures:

(a) printing;

(b) coating;

(c) additive manufacturing;

(d) dispensing.

4. The method as set forth in claim 3 , wherein the encapsulation material is not suitable to be applied under external pressure.

5. The method as set forth in claim 3 , wherein the first stack represents a first portion of a component carrier, and the encapsulation material represents a second portion of the component carrier.

6. The method as set forth in claim 5 , wherein the electronic package is a hybrid structure comprising the first stack as a printed circuit board structure and the encapsulation material as a non-printed circuit board structure.

7. The method as set forth in claim 1 , wherein placing the electronic component comprises bonding the electronic component to the layer structure.

8. The method as set forth in claim 1 , wherein the electronic component is encapsulated together with at least one further electronic component which, after a singularizing process, forms a part of a further electronic package.

9. The method as set forth in claim 1 , wherein the layer structure comprises at least one electrically conductive layer structure and/or the at least one further layer structure comprises at least one electrically insulating layer structure.

10. The method as set forth in claim 1 , further comprising:

a further encapsulant surrounding the encapsulation material, the further encapsulant being different from the encapsulation material, wherein the further encapsulant comprises an electrically conductive material.

11. The method as set forth in claim 10 , wherein the encapsulation material encapsulating the electronic component and/or the further encapsulant surrounding the encapsulation material have a planar surface, wherein the planar surface is opposite to the stack.

12. The method as set forth in claim 10 , wherein the electronic package comprises at least one of the following features:

the electronic package further comprises a wiring structure being embedded within the encapsulation material and/or within the further encapsulant, the wiring structure being configured for electrically connecting the electronic component;

the surface protection layer structure which is formed beneath the stack or forms a part of the stack.

13. The method as set forth in claim 1 , wherein the surface protection layer structure substantially covers the whole bottom of the electrically conductive structure of the first stack.

14. The method as set forth in claim 1 , wherein the surface protection layer structure is configured to prevent oxidation of the bottom surface of the electrically conductive structure of the first stack.

15. The method as set forth in claim 1 , wherein the surface protection layer structure is electrically conductive.