IP Library › Granted Patent US 11,595,039
Granted Patent B2
US 11,595,039 · App. 17/658,016 · Granted Feb 28, 2023

Power switching circuit and corresponding method of operation

Inventors: Noemi Gallo (Milan, IT); Edoardo Botti (Pavia, IT)
Assignee: STMicroelectronics S.r.l.
H03K17/56H03K17/687H03K19/20H03K2217/0063H03K2217/0072
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Quick Facts
Patent No.
US 11,595,039
App. No.
17/658,016
Granted
Feb 28, 2023
Kind
B2
Abstract

A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

Claims (85)

1. A circuit, comprising:

a high-side switch coupled between a first supply voltage rail and an output node;

a low-side switch coupled between the output node and a first reference voltage rail;

a first inverter arrangement configured to receive a high-side control signal and to produce a high-side gate control signal for the high-side switch, the first inverter arrangement comprising:

a first discharge current path between a control terminal of the high-side switch and a second reference voltage rail, the first discharge current path being activatable to sink a first discharge current from the control terminal of the high-side switch; and

a second discharge current path between the control terminal of the high-side switch and the second reference voltage rail, the second discharge current path being activatable to sink a second discharge current from the control terminal of the high-side switch;

a second inverter arrangement configured to receive a low-side control signal and to produce a low-side gate control signal for the low-side switch, the second inverter arrangement comprising:

a first charge current path between a control terminal of the low-side switch and a second supply voltage rail, the first charge current path being activatable to source a first charge current to the control terminal of the low-side switch; and

a second charge current path between the control terminal of the low-side switch and the second supply voltage rail, the second charge current path being activatable to source a second charge current to the control terminal of the low-side switch;

a high-side sensing current path arranged between the first supply voltage rail and the second reference voltage rail, the high-side sensing current path comprising:

a high-side sensing transistor having a first current path coupled between the first supply voltage rail and an intermediate high-side control node, and a gate terminal coupled to the control terminal of the high-side switch; and

a first high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a first high-side reference current from the intermediate high-side control node; and

a low-side sensing current path arranged between the first reference voltage rail and the second supply voltage rail, the low-side sensing current path comprising:

a low-side sensing transistor having a second current path coupled between the first reference voltage rail and an intermediate low-side control node, and a gate terminal coupled to the control terminal of the low-side switch; and

a first low-side current source coupled between the intermediate low-side control node and the second supply voltage rail to source a first low-side reference current to the intermediate low-side control node;

wherein the second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

2. The circuit of claim 1 , wherein:

the second discharge current path comprises a high-side control transistor having a first control terminal coupled to the intermediate high-side control node and configured to selectively enable the second discharge current path; and

the second charge current path comprises a low-side control transistor having a second control terminal coupled to the intermediate low-side control node and configured to selectively enable the second charge current path.

3. The circuit of claim 1 , wherein:

the high-side sensing current path comprises a second high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a second high-side reference current from the intermediate high-side control node, the second high-side current source being enabled in response to the high-side detection signal at the intermediate high-side control node having the low logic value; and

the low-side sensing current path comprises a second low-side current source coupled between the intermediate low-side control node and the second supply voltage rail to source a second low-side reference current to the intermediate low-side control node, the second low-side current source being enabled in response to the low-side detection signal at the intermediate low-side control node having the high logic value.

4. The circuit of claim 1 , wherein the first discharge current is lower than the second discharge current, and/or the first charge current is lower than the second charge current.

5. The circuit of claim 1 , wherein the high-side switch comprises a high-side power transistor, and the low-side switch comprises a low-side power transistor.

6. The circuit of claim 5 , wherein the high-side power transistor is a p-channel metal-oxide-semiconductor (MOS) transistor, and the low-side power transistor is an n-channel MOS transistor.

7. The circuit of claim 5 , wherein the high-side sensing transistor is of the same type as and has smaller dimensions than the high-side power transistor, and the low-side sensing transistor is of the same type as and has smaller dimensions than the low-side power transistor.

8. The circuit of claim 1 , comprising:

an input node configured to receive a pulse-width modulated driving signal;

an OR logic gate configured to combine the pulse-width modulated driving signal and an inverted replica of the low-side detection signal;

a first inverter circuit coupled to an output of the OR logic gate to produce the high-side control signal;

an AND logic gate configured to combine the pulse-width modulated driving signal and an inverted replica of the high-side detection signal; and

a second inverter circuit coupled to an output of the AND logic gate to produce the low-side control signal.

9. A method of operating a circuit comprising a high-side switch coupled between a first supply voltage rail and an output node, a low-side switch coupled between the output node and a first reference voltage rail, a high-side sensing transistor having a first current path coupled between the first supply voltage rail and an intermediate high-side control node, and a low-side sensing transistor having a second current path coupled between the first reference voltage rail and an intermediate low-side control node, the method comprising:

receiving a high-side control signal and producing a high-side gate control signal for the high-side switch, the producing the high-side gate control signal comprising:

sourcing a charge current to a control terminal of the high-side switch in response to the high-side control signal having a low logic value; and

sinking a first discharge current from the control terminal of the high-side switch in response to the high-side control signal having a high logic value;

receiving a low-side control signal and producing a low-side gate control signal for the low-side switch, the producing the low-side gate control signal comprising:

sinking a discharge current from a control terminal of the low-side switch in response to the low-side control signal having the high logic value; and

sourcing a first charge current to the control terminal of the low-side switch in response to the low-side control signal having the low logic value;

producing a high-side detection signal at the intermediate high-side control node, the producing the high-side detection signal comprising sourcing a current to the intermediate high-side control node in response to the high-side switch being in a conductive state, and sinking a first high-side reference current from the intermediate high-side control node;

producing a low-side detection signal at the intermediate low-side control node, the producing the low-side detection signal comprises sinking a current from the intermediate low-side control node in response to the low-side switch being in the conductive state, and sourcing a first low-side reference current to the intermediate low-side control node;

sinking a second discharge current from the control terminal of the high-side switch in response to the high-side control signal having the high logic value and the high-side detection signal having the high logic value; and

sourcing a second charge current to the control terminal of the low-side switch in response to the low-side control signal having the low logic value and the low-side detection signal having the low logic value.

10. The method of claim 9 , wherein the circuit further comprises a first discharge current path between a control terminal of the high-side switch and a second reference voltage rail, a second discharge current path between the control terminal of the high-side switch and the second reference voltage rail, a first charge current path between a control terminal of the low-side switch and a second supply voltage rail, and a second charge current path between the control terminal of the low-side switch and the second supply voltage rail, and the method further comprises:

selectively enabling, by a high-side control transistor having a first control terminal coupled to the intermediate high-side control node, the second discharge current path; and

selectively enabling, by a low-side control transistor having a second control terminal coupled to the intermediate low-side control node, the second charge current path.

11. The method of claim 9 , further comprising:

enabling a second high-side current source in response to the high-side detection signal at the intermediate high-side control node having the low logic value; and

enabling a second low-side current source in response to the low-side detection signal at the intermediate low-side control node having the high logic value.

12. The method of claim 11 , further comprising:

sinking, by the second high-side current source coupled between the intermediate high-side control node and a second reference voltage rail in the high-side sensing current path, a second high-side reference current from the intermediate high-side control node; and

sourcing, by the second low-side current source coupled between the intermediate low-side control node and a second supply voltage rail in the low-side sensing current path, a second low-side reference current to the intermediate low-side control node.

13. The method of claim 9 , wherein the first discharge current is lower than the second discharge current, and/or the first charge current is lower than the second charge current.

14. The method of claim 9 , comprising:

receiving, by an input node, a pulse-width modulated driving signal;

combining, by an OR logic gate, the pulse-width modulated driving signal and an inverted replica of the low-side detection signal;

producing, by a first inverter circuit coupled to an output of the OR logic gate, the high-side control signal;

combining, by an AND logic gate, the pulse-width modulated driving signal and an inverted replica of the high-side detection signal; and

producing, by a second inverter circuit coupled to an output of the AND logic gate, the low-side control signal.

15. A circuit, comprising:

a high-side switch coupled between a first supply voltage rail and an output node;

a low-side switch coupled between the output node and a first reference voltage rail;

a first discharge current path between a control terminal of the high-side switch and a second reference voltage rail, the first discharge current path being activatable to sink a first discharge current from the control terminal of the high-side switch;

a second discharge current path between the control terminal of the high-side switch and the second reference voltage rail, the second discharge current path being activatable to sink a second discharge current from the control terminal of the high-side switch;

a first charge current path between a control terminal of the low-side switch and a second supply voltage rail, the first charge current path being activatable to source a first charge current to the control terminal of the low-side switch;

a second charge current path between the control terminal of the low-side switch and the second supply voltage rail, the second charge current path being activatable to source a second charge current to the control terminal of the low-side switch;

a high-side sensing transistor having a first current path coupled between the first supply voltage rail and an intermediate high-side control node, and a gate terminal coupled to the control terminal of the high-side switch;

a first high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a first high-side reference current from the intermediate high-side control node;

a low-side sensing transistor having a second current path coupled between the first reference voltage rail and an intermediate low-side control node, and a gate terminal coupled to the control terminal of the low-side switch; and

a first low-side current source coupled between the intermediate low-side control node and the second supply voltage rail to source a first low-side reference current to the intermediate low-side control node;

wherein the second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

16. The circuit of claim 15 , wherein:

the second discharge current path comprises a high-side control transistor having a first control terminal coupled to the intermediate high-side control node and configured to selectively enable the second discharge current path; and

the second charge current path comprises a low-side control transistor having a second control terminal coupled to the intermediate low-side control node and configured to selectively enable the second charge current path.

17. The circuit of claim 15 , wherein:

a high-side sensing current path comprises a second high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a second high-side reference current from the intermediate high-side control node, the second high-side current source being enabled in response to the high-side detection signal at the intermediate high-side control node having the low logic value; and

a low-side sensing current path comprises a second low-side current source coupled between the intermediate low-side control node and the second supply voltage rail to source a second low-side reference current to the intermediate low-side control node, the second low-side current source being enabled in response to the low-side detection signal at the intermediate low-side control node having the high logic value.

18. The circuit of claim 15 , wherein the first discharge current is lower than the second discharge current, and/or the first charge current is lower than the second charge current.

19. The circuit of claim 15 , wherein the high-side switch comprises a high-side power transistor, and the low-side switch comprises a low-side power transistor.

20. The circuit of claim 15 , comprising:

an input node configured to receive a pulse-width modulated driving signal;

an OR logic gate configured to combine the pulse-width modulated driving signal and an inverted replica of the low-side detection signal;

a first inverter circuit coupled to an output of the OR logic gate to produce a high-side control signal;

an AND logic gate configured to combine the pulse-width modulated driving signal and an inverted replica of the high-side detection signal; and

a second inverter circuit coupled to an output of the AND logic gate to produce a low-side control signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2022
From: GALLO, NOEMI; BOTTI, EDOARDO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 059504/0870 →
Priority Claims (1)
IT 102021000009773 · Apr 19, 2021 · national
Continuity (1)
Related Publication 20220337236A1 · Oct 20, 2022
Cited By (1)
US 12,609,660