Inter-die memory-bus transaction in a seamlessly integrated microcontroller chip
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
1. A system, comprising:
a first die, comprising:
a first bus;
a central processing unit (CPU) configured as a first master on the first bus;
a second master configured as a second master on the first bus; and
a first bridge configured to communicate with a second die; and
a second die electrically coupled to the first die by die-to-die interconnects, wherein the second die comprises:
a second bridge configured to communicate with the first die, wherein the die-to-die interconnects are selectively shared by the first die and the second die,
wherein the system is configured to perform a memory-mapped bus transaction so that the memory-mapped bus transaction appears as though it is implemented on the first die to the CPU and the second master, and
wherein, when there is an incomplete memory-mapped bus transaction initiated by the first master or the second master, the second die is configured to pause the incomplete memory-mapped bus transaction and allow the first master or the second master to perform another transaction.
2. The system of claim 1 , wherein second master comprises a direct memory access (DMA) controller.
3. The system of claim 2 , wherein the DMA controller comprises a DMA request input synchronized between the first die and the second die via the die-to-die interconnects.
4. The system of claim 3 , wherein the DMA request input is synchronized on a cycle-accurate basis during memory-mapped data operations in the memory-mapped bus transaction.
5. The system of claim 2 , wherein DMA activations are propagated as unrelated to the memory-mapped bus transaction.
6. The system of claim 2 , wherein the system is configured to provide DMA request updates as part of the memory-mapped bus transaction or as part of a data phase of the memory-mapped bus transaction.
7. The system of claim 2 , wherein an input to the DMA controller is updated as data is transferred during the memory-mapped bus transaction.
8. The system of claim 1 , wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die.
9. The system of claim 1 , wherein the second die is configured to pause the incomplete memory-mapped bus transaction when the incomplete memory-mapped bus transaction has been pending completion for more than a time interval or is estimated to be pending completion for more than the time interval.
10. A method for performing a memory-mapped bus transaction, comprising:
providing, from a second bridge in a second die, die-to-die interconnect signals via die-to-die interconnects between the second die and a first die, wherein the die-to-die interconnects are selectively shared by the first die and the second die, and wherein the first die comprises: a central processing unit (CPU) that is a first master on a first bus in the first die; and a second master that is a second master on the first bus;
performing the memory-mapped bus transaction so that the memory-mapped bus transaction appears as though it is implemented on the first die to the CPU and the second master; and
when there is an incomplete memory-mapped transaction initiated by the first master or the second master, pausing, by the second die, the incomplete memory-mapped transaction and allowing the first master or the second master to perform another transaction.
11. The method of claim 10 , wherein second master comprises a direct memory access (DMA) controller.
12. The method of claim 11 , wherein the DMA controller comprises a DMA request input synchronized between the first die and the second die via the die-to-die interconnects.
13. The method of claim 12 , wherein the DMA request input is synchronized on a cycle-accurate basis during memory-mapped data operations in the memory-mapped bus transaction.
14. The method of claim 11 , wherein DMA activations are propagated as unrelated to the memory-mapped bus transaction.
15. The method of claim 11 , wherein the method comprises providing DMA request updates as part of the memory-mapped bus transaction or as part of a data phase of the memory-mapped bus transaction.
16. The method of claim 11 , wherein an input to the DMA controller is updated as data is transferred during the memory-mapped bus transaction.
17. The method of claim 10 , wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die.
18. The method of claim 10 , wherein the pausing of the incomplete memory-mapped transaction occurs when the incomplete memory-mapped transaction has been pending completion for more than a time interval or is estimated to be pending completion for more than the time interval.
19. An electronic device, comprising:
a first die, comprising:
a first bus;
a central processing unit (CPU) configured as a first master on the first bus;
a second master configured as a second master on the first bus; and
a first bridge configured to communicate with a second die; and
a second die electrically coupled to the first die by die-to-die interconnects, wherein the second die comprises:
a second bridge configured to communicate with the first die, wherein the die-to-die interconnects are selectively shared by the first die and the second die, and
wherein the system is configured to perform a memory-mapped bus transaction so that the memory-mapped bus transaction appears as though it is implemented on the first die to the CPU and the second master, and
wherein, when there is an incomplete memory-mapped bus transaction initiated by the first master or the second master, the second die is configured to pause the incomplete memory-mapped bus transaction and allow the first master or the second master to perform another transaction.
20. The electronic device of claim 19 , wherein second master comprises a direct memory access (DMA) controller.