IP Library Granted Patent US 11,601,056
Granted Patent B2
US 11,601,056 · App. 17/384,944 · Granted Mar 7, 2023

Hybrid architecture for DC-DC conversion

Inventor: Santosh Kulkarni (Swindon, GB)
Assignee: Dialog Semiconductor (UK) Limited
H02M3/1582H02M1/007H02M1/0095H02M1/08
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Quick Facts
Patent No.
US 11,601,056
App. No.
17/384,944
Granted
Mar 7, 2023
Kind
B2
Abstract

A Hybrid DC-DC switching converter architecture is described. The Hybrid architecture includes a capacitive converter cascaded by an inductive converter for a boost switching converter, and an inductive converter cascaded by a capacitive converter for a buck switching converter. A capacitor at an intermediate node and a switch in the capacitive converter are removed. Reducing the switching converter by one switch and one capacitor results in a smaller implementation area. A single regulation circuit and an inductor with a smaller saturation current (Isat) are used.

Claims (56)

1. A Hybrid DC-DC boost switching converter architecture, comprising:

a first stage, comprising a capacitive converter, wherein the capacitive converter comprises a plurality of switches and a capacitor,

wherein the plurality of switches and the capacitor comprises:

a first resistor between an input voltage and a first node of a first switch, and a second resistor between the input voltage and a first node of a second switch;

a first capacitor connected between an intermediate node, which is also a second node of the first switch, and a first node of a third switch, which is also a second node of the second switch; and

a third resistor between a second node of the third switch and a reference terminal (e.g. ground);

a second stage, comprising an inductive converter; and

wherein the first stage is cascaded by the second stage.

2. The boost switching converter architecture of claim 1 , wherein the inductive converter comprises:

a fourth resistor between the intermediate node and a first node of an inductor;

a first node of a fourth switch between a second node of the inductor and a fifth resistor, a sixth resistor between the second node of the inductor and a first node of a fifth switch; and

a second capacitor between a second node of the fifth switch (which is also an output voltage) and a reference terminal (e.g. ground).

3. The boost switching converter architecture of claim 1 , wherein the first and second stages are regulated with a single control circuit.

4. The switching converter architecture of claim 1 , wherein the switches are configured to operate with fixed pulse waveforms.

5. The switching converter architecture of claim 1 , wherein an amount of current driven through the switching converter is a multiple of a current driven in the first stage.

6. The switching converter architecture of claim 1 , wherein the first and second stages are regulated with current mode control.

7. The switching converter architecture of claim 1 , wherein the first and second stages are regulated with voltage mode control.

8. A Hybrid DC-DC buck switching converter architecture, comprising:

a first stage, comprising an inductive converter;

a second stage, comprising a capacitive converter, the capacitive converter comprising a plurality of switches and a capacitor,

wherein the plurality of switches and the capacitor comprises:

a first resistor between an input voltage and a first node of a first switch, and a second resistor between the input voltage and a first node of a second switch;

a first capacitor connected between an intermediate node, which is also a second node of the first switch, and a first node of a third switch, which is also a second node of the second switch; and

a third resistor between a second node of the third switch and a reference terminal (e.g. ground);

and wherein the first stage is cascaded by the second stage.

9. The buck switching converter architecture of claim 8 , wherein the inductive converter comprises:

a first switch connected between an input voltage and a first node of an inductor, which is also a first node of a second switch, connected between the second node of the first switch and a reference terminal (e.g. ground).

10. The buck switching converter architecture of claim 8 , wherein the plurality of switches and the capacitor comprises:

a first capacitor connected between an intermediate node, which is also a second node of the inductor, and a first node of a third switch, which is also a first node of a fourth switch; and

a fifth switch connected between the intermediate node and a second node of the fourth switch, which is also a first node of a second capacitor (and an output voltage).

11. The boost switching converter architecture of claim 8 , wherein the first and second stages are regulated with a single control circuit.

12. The switching converter architecture of claim 8 , wherein the switches are configured to operate with fixed pulse waveforms.

13. The switching converter architecture of claim 8 , wherein the capacitor converter further comprises a series-parallel, Dickson, ladder, doubler, or Fibonacci arrangement.

14. The switching converter architecture of claim 8 , wherein the first and second stages are regulated with current mode control.

15. The switching converter architecture of claim 8 , wherein the first and second stages are regulated with voltage mode control.

16. A method for a Hybrid DC-DC boost switching converter architecture, comprising:

cascading a first stage, comprising a plurality of switches and a capacitor,

wherein the plurality of switches and the capacitor comprises:

a first resistor between an input voltage and a first node of a first switch, and a second resistor between the input voltage and a first node of a second switch;

a first capacitor connected between an intermediate node, which is also a second node of the first switch, and a first node of a third switch, which is also a second node of the second switch; and

a third resistor between a second node of the third switch and a reference terminal (e.g. ground);

by a second stage, comprising an inductive converter.

17. The method of claim 16 , wherein regulating the first and second stages of the hybrid DC-DC switching converter with a single control circuit.

18. The method of claim 16 , wherein a multiple of a current driven in the first stage determines an amount of current driven through the switching converter.

19. The method of claim 16 , wherein current mode control is used in the single control circuit.

20. The method of claim 16 , wherein voltage mode control is used in the single control circuit.

21. A method for a Hybrid DC-DC buck switching converter architecture, comprising:

cascading a first stage, comprising an inductive converter, by a second stage, comprising a plurality of switches and a capacitor,

wherein the plurality of switches and the capacitor comprises:

a first resistor between an input voltage and a first node of a first switch, and a second resistor between the input voltage and a first node of a second switch;

a first capacitor connected between an intermediate node, which is also a second node of the first switch, and a first node of a third switch, which is also a second node of the second switch; and

a third resistor between a second node of the third switch and a reference terminal (e.g. ground).

22. The method of claim 21 , wherein regulating the first and second stages of the hybrid DC-DC switching converter with a single control circuit.

23. The method of claim 21 , wherein the second stage further comprises a series-parallel, Dickson, ladder, doubler, or Fibonacci arrangement.

24. The method of claim 21 , wherein current mode control is used in the single control circuit.

25. The method of claim 21 , wherein voltage mode control is used in the single control circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2021
From: KULKARNI, SANTOSH
To: DIALOG SEMICONDUCTOR (UK) LIMITED
Reel/Frame 057704/0926 →
Continuity (1)
Related Publication 20230026364A1 · Jan 26, 2023