Imaging device and method of operating the same
An imaging device includes an image sensing circuitry configured to receive image signals from pixels, to convert the received image signals into image data, and to output the image data. The imaging device includes a digital processing circuitry configured to process image data in synchronization with a digital clock. The digital processing circuitry includes a digital clock generator configured to generate the digital clock. The digital clock generator is configured to scatter the digital clock, in response to the image sensing circuitry converting the image signals into the image data.
1. An imaging device, comprising:
an image sensing circuitry configured to receive image signals from pixels, to convert the received image signals into image data, and to output the image data; and
a digital processing circuitry configured to process the image data in synchronization with a digital clock,
wherein the digital processing circuitry includes a digital clock generator configured to generate the digital clock, and
wherein the digital clock generator is configured to scatter the digital clock, in response to the image sensing circuitry converting the image signals into the image data.
2. The imaging device of claim 1 , wherein the image sensing circuitry includes
an analog-to-digital conversion circuit configured to convert the received image signals into the image data based on comparing the image signals with a ramp signal and performing counting operations corresponding to results of the comparison; and
a timing controller configured to generate a counter enable signal related to the counting operations.
3. The imaging device of claim 2 , wherein the digital clock generator is configured to scatter the digital clock according to a particular timing sequence in response to the counter enable signal.
4. The imaging device of claim 2 , wherein the digital clock generator is configured to scatter the digital clock according to a particular timing sequence in response to a horizontal synchronization signal of the timing controller.
5. The imaging device of claim 1 , wherein
the image sensing circuitry is configured to perform a first analog-to-digital conversion (ADC) operation corresponding to a reset voltage and perform a second ADC operation corresponding to a pixel voltage, and
the digital clock generator is configured to gate the digital clock in an entire or partial period of each of
a first ADC period corresponding to the first ADC operation, and
a second ADC period corresponding to the second ADC operation.
6. The imaging device of claim 1 , wherein
the image sensing circuitry is configured to perform a first analog-to-digital conversion (ADC) operation corresponding to a reset voltage and perform a second ADC operation corresponding to a pixel voltage, and
the digital clock generator is configured to divide the digital clock in an entire or partial period of each of
a first ADC period corresponding to the first ADC operation, and
a second ADC period corresponding to the second ADC operation.
7. The imaging device of claim 1 , wherein
the image sensing circuitry is configured to perform a first analog-to-digital conversion (ADC) operation corresponding to a reset voltage and perform a second ADC operation corresponding to a pixel voltage, and
the digital clock generator is configured to
gate the digital clock in a partial period of each of a first ADC period corresponding to the first ADC operation, and a second ADC period corresponding to the second ADC operation, and
divide the digital clock in another period of each of the first ADC period and the second ADC period.
8. The imaging device of claim 1 , wherein
the image sensing circuitry is configured to perform a first analog-to-digital conversion (ADC) operation corresponding to a reset voltage and perform a second ADC operation corresponding to a pixel voltage, and
the digital clock generator is configured to scatter the digital clock in
a first stall period including a first ADC period corresponding to the first ADC operation, and
a second stall period including a second ADC period corresponding to the second ADC operation.
9. The imaging device of claim 8 , wherein
each of the first ADC period and the second ADC period is divided into a plurality of clock scattering periods, and
in the plurality of clock scattering periods, the digital clock is scattered by different schemes.
10. The imaging device of claim 8 , wherein
each of the first ADC period and the second ADC period is divided into a plurality of clock scattering periods, and
in at least two of the plurality of clock scattering periods, the digital clock is divided according to different clock division ratios.
11. A method of operating an imaging device, the method comprising:
converting an image signal into image data based on performing a counting operation until the image signal and a ramp signal equalize; and
reducing consumption of digital power using a clock scattering scheme in response to the counting operation being performed.
12. The method of claim 11 , wherein the clock scattering scheme includes gating or dividing a digital clock used in an image sensing circuitry of the imaging device or a digital processing circuitry of the imaging device.
13. The method of claim 12 , wherein
the converting into the image data includes performing a first analog-to-digital (ADC) operation corresponding to a reset voltage, and performing a second ADC operation corresponding to a pixel voltage, and
the reducing the consumption of the digital power includes gating or dividing the digital clock in an entire or partial period of a first ADC period corresponding to the first ADC operation and a second ADC period corresponding to the second ADC operation.
14. The method of claim 13 , further comprising:
transmitting the image data to a plurality of image signal processors connected to each other in series,
wherein each of the plurality of image signal processors does not process data processed in a first stall period corresponding to the first ADC operation and a second stall period corresponding to the second ADC operation.
15. The method of claim 11 , wherein, in the clock scattering scheme, a clock gating period, a clock division period, or a clock division ratio is determined based on a user setting.
16. An imaging device, comprising:
a pixel array having a plurality of pixels arranged in a plurality of row lines and a plurality of column lines;
a row driver configured to select one row line of the plurality of row lines;
an analog-to-digital conversion circuit configured to covert analog signals output by the pixel array into digital data;
a digital clock generator configured to generate a transfer clock for transmitting the digital data to an image signal processor; and
a timing controller configured to control timing of the pixel array, the row driver, the analog-to-digital conversion circuit, and the digital clock generator,
wherein the analog-to-digital conversion circuit includes a comparator circuit having comparators for comparing pixel signals output by the pixel array with a ramp signal, and a counter circuit having counters configured to count an output of each comparator of the comparators, and
wherein the digital clock generator is configured to scatter the transfer clock in response to a horizontal synchronization signal or a counter enable signal received from the timing controller.
17. The imaging device of claim 16 , wherein the digital clock generator is configured to gate or divide the transfer clock in response to the counters being enabled.
18. The imaging device of claim 16 , wherein scattering of the transfer clock is determined according to a user setting.
19. The imaging device of claim 16 , wherein the transfer clock is scattered based on a gated clock scheme or a divided clock scheme.
20. The imaging device of claim 19 , wherein the transfer clock is scattered based on the gated clock scheme or the divided clock scheme in a partial or entire period in which the counters are enabled.