Error correction in row hammer mitigation and target row refresh
Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.
1. A method comprising:
initiating a refresh operation on a target row in which are stored a plurality of code words, wherein the refresh operation includes reading the plurality of code words into a buffer;
performing an error checking operation on a subset of the plurality of code words;
correcting an error in one code word of the subset by overwriting the one code word in the buffer with a corrected code word; and
completing the refresh operation by writing back the plurality of code words, including the corrected code word, from the buffer to the target row.
2. The method of claim 1 , wherein the subset includes a single code word of the plurality of code words.
3. The method of claim 1 , wherein the subset includes more than one, but less than all, of the plurality of code words.
4. The method of claim 1 , further comprising identifying a row hammer condition in the target memory row, and wherein initiating the memory refresh operation is performed in response to identifying the row hammer condition.
5. The method of claim 4 , wherein the row hammer condition in the target memory row is associated with a particular row identified as having potential leakage and wherein the target memory row is a row adjacent to the particular row.
6. The method of claim 1 , further comprising updating tracking data stored in relation to the target row indicating the error correction operation has been performed on the subset.
7. The method of claim 1 , wherein the target memory row comprises a row of an array within a dynamic random-access memory (DRAM) device.
8. A system comprising:
a memory array;
circuitry configured to:
initiate a refresh operation on a target row in which are stored a plurality of code words, wherein the refresh operation includes reading the plurality of code words into a buffer;
perform an error checking operation on a subset of the plurality of code words;
correct an error in one code word of the subset by overwriting the one code word in the buffer with a corrected code word; and
complete the refresh operation by writing back the plurality of code words, including the corrected code word, from the buffer to the target row.
9. The system of claim 8 , wherein the subset includes a single code word of the plurality of code words.
10. The system of claim 8 , wherein the subset includes more than one, but less than all, of the plurality of code words.
11. The system of claim 8 , wherein the circuitry is further configured to identify a row hammer condition in the target memory row, and to initiate the memory refresh operation in response to identifying the row hammer condition.
12. The system of claim 11 , wherein the row hammer condition in the target memory row is associated with a particular row identified as having potential leakage and wherein the target memory row is a row adjacent to the particular row.
13. The system of claim 8 , wherein the circuitry is further configured to update tracking data stored in relation to the target row indicating the error correction operation has been performed on the subset.
14. The system of claim 8 , wherein the target memory row comprises a row of an array within a dynamic random-access memory (DRAM) device.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processing devices, cause the one or more processing devices to:
initiate a refresh operation on a target row in which are stored a plurality of code words, wherein the refresh operation includes reading the plurality of code words into a buffer;
perform an error checking operation on a subset of the plurality of code words;
correct an error in one code word of the subset by overwriting the one code word in the buffer with a corrected code word; and
complete the refresh operation by writing back the plurality of code words, including the corrected code word, from the buffer to the target row.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the subset includes a single code word of the plurality of code words.
17. The non-transitory computer-readable storage medium of claim 16 , wherein the subset includes more than one, but less than all, of the plurality of code words.
18. The non-transitory computer-readable storage medium of claim 17 , wherein the instructions, when executed by the one or more processing devices, further cause the one or more processing devices to identify a row hammer condition in the target memory row, and to initiate the memory refresh operation in response to identifying the row hammer condition.
19. The non-transitory computer-readable storage medium of claim 18 , wherein the row hammer condition in the target memory row is associated with a particular row identified as having potential leakage and wherein the target memory row is a row adjacent to the particular row.
20. The non-transitory computer-readable storage medium of claim 15 , wherein the instructions, when executed by the one or more processing devices, further cause the one or more processing devices to update tracking data stored in relation to the target row indicating the error correction operation has been performed on the subset.