IP Library Granted Patent US 11,611,004
Granted Patent B2
US 11,611,004 · App. 16/608,801 · Granted Mar 21, 2023

Opto-electronic integrated circuit and computing apparatus

Inventors: Takeru Amano (Ibaraki, JP); Akihiro Noriki (Ibaraki, JP)
Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
H01L31/0232G02B6/43H01S5/022H01L27/15
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Quick Facts
Patent No.
US 11,611,004
App. No.
16/608,801
Granted
Mar 21, 2023
Kind
B2
Abstract

A circuit board ( 100 ) has a first surface ( 102 ). A semiconductor chip ( 200 ) (first semiconductor chip) is located at the first surface side ( 102 ) of the circuit board ( 100 ). An insulating layer ( 300 ) covers the first surface ( 102 ) of the circuit board ( 100 ) and the semiconductor chip ( 200 ). A conductive path ( 310 ) (first conductive path) is electrically connected to the semiconductor chip ( 200 ) and extends in the insulating layer ( 300 ). A waveguide ( 320 ) is optically coupled to the semiconductor chip ( 200 ) and extends in the insulating layer ( 300 ).

Claims (26)

1. An opto-electronic integrated circuit comprising:

a circuit board having a first surface;

a first semiconductor chip buried into the first surface of the circuit board and bonded to the circuit board through a mold material;

an insulating layer covering the first surface of the circuit board and the first semiconductor chip;

a waveguide optically coupled to the first semiconductor chip and extending in the insulating layer; and

a first via electrically connected to the first semiconductor chip, the first via being buried into a first portion of the insulating layer, the first portion of the insulating layer overlapping the first semiconductor chip.

2. The opto-electronic integrated circuit according to claim 1 , further comprising:

a second semiconductor chip over the insulating layer; and a second via electrically connected to the second semiconductor chip, the second via being buried into a second portion of the insulating layer, the second portion of the insulating layer overlapping the second semiconductor chip,

wherein the first via and the second via are electrically connected to each other.

3. The opto-electronic integrated circuit according to claim 2 , further comprising:

a third via electrically connected to the circuit board, the third via being buried into a third portion of the insulating layer, the third portion of the insulating layer overlapping the circuit board, the first via and third via being arranged in a predetermined direction;

a fourth via electrically connected to the second semiconductor chip, the fourth via being buried into a fourth portion of the insulating layer, the fourth portion of the insulating layer being overlapping the second semiconductor chip, the second via and the fourth via being arranged in the predetermined direction,

wherein the third via and the fourth via are electrically connected to each other,

wherein a distance between the second via and the fourth via in the predetermined direction is shorter than a distance between first via and the third via in the predetermined direction.

4. A computing device comprising:

a system board having a main surface; and

an opto-electronic integrated circuit located over the main surface of the system board,

wherein the opto-electronic integrated circuit comprises:

a circuit board having a first surface and a second surface opposite to the first surface, the circuit board being mounted over the system board such that the second surface faces the main surface of the system board;

a first semiconductor chip buried into the first surface of the circuit board and bonded to the circuit board through a mold material;

an insulating layer covering the first surface of the circuit board and the first semiconductor chip;

a waveguide optically coupled to the first semiconductor chip and extending in the insulating layer; and

a first via electrically connected to the first semiconductor chip, the first via being buried into a first portion of the insulating layer, the first portion of the insulating layer overlapping the first semiconductor chip.

5. The opto-electronic integrated circuit according to claim 1 , further comprising:

a second semiconductor chip over the insulating layer,

wherein the first semiconductor chip and the second semiconductor chip are electrically connected through the first via.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2022
From: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
To: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
Reel/Frame 061248/0569 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2019
From: AMANO, TAKERU; NORIKI, AKIHIRO
To: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY; PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
Reel/Frame 050834/0153 →
Priority Claims (1)
JP JP2017-089878 · Apr 28, 2017 · national
Continuity (1)
Related Publication 20210104637A1 · Apr 8, 2021
Cited By (1)
US 12,710,604