IP Library Granted Patent US 11,612,057
Granted Patent B2
US 11,612,057 · App. 17/815,373 · Granted Mar 21, 2023

Opening in the pad for bonding integrated passive device in InFO package

Inventors: Cheng-Hsien Hsieh (Kaohsiung, TW); Chi-Hsi Wu (Hsinchu, TW); Chen-Hua Yu (Hsinchu, TW); Der-Chyang Yeh (Hsinchu, TW); Hsien-Wei Chen (Hsinchu, TW); Li-Han Hsu (Hsinchu, TW); Wei-Cheng Wu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H05K1/115H01L24/19H01L24/20H05K1/111H05K1/113H05K1/181H01L2224/04105H01L2224/12105H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/73265H01L2224/73267H01L2924/15311H01L2924/181H05K1/0271H05K2201/0183H05K2201/068H05K2201/0969H05K2201/09136H05K2201/09381
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Quick Facts
Patent No.
US 11,612,057
App. No.
17/815,373
Granted
Mar 21, 2023
Kind
B2
Abstract

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Claims (45)

1. A package comprising:

a dielectric layer;

a plurality of conductive pads in the dielectric layer;

an Under-Bump Metallurgy (UBM) comprising:

a plurality of via portions extending into the dielectric layer, wherein each of the plurality of via portions lands on one of the plurality of conductive pads; and

a pad portion higher than the dielectric layer, wherein the pad portion is continuously joined with the plurality of via portions;

a solder region over and contacting the pad portion of the UBM; and

an integrated passive device, wherein the solder region bonds the UBM to the integrated passive device.

2. The package of claim 1 , wherein no distinguishable interface is formed between the pad portion and the plurality of via portions.

3. The package of claim 1 , wherein the dielectric layer extends into one of the plurality of conductive pads to form a plurality of dielectric plugs.

4. The package of claim 3 , wherein the plurality of dielectric plugs penetrate through the one of the plurality of conductive pads.

5. The package of claim 3 , wherein the plurality of dielectric plugs are arranged as an array.

6. The package of claim 3 , wherein in a top view of the package, the plurality of dielectric plugs are aligned to a plurality of rings, each encircling one of the plurality of via portions.

7. The package of claim 1 further comprising:

a plurality of redistribution lines underlying the plurality of conductive pads;

a molding compound underlying the plurality of redistribution lines; and

a device die molded in the molding compound.

8. The package of claim 1 , wherein the integrated passive device comprises a terminal joined to the solder region.

9. The package of claim 1 , wherein the UBM has an elongated top view shape, with the plurality of via portions being aligned to a straight line.

10. The package of claim 1 , wherein each of plurality of conductive pads extends laterally beyond a respective edge of the UBM.

11. A package comprising:

a two-terminal passive device die comprising:

a first terminal; and

a second terminal;

a solder region underlying and joined to the first terminal; and

a conductive feature underlying and joined to the solder region, the conductive feature comprising:

a pad portion underlying and electrically coupling to the first terminal; and

a plurality of via portions underlying and physically joined to the pad portion; and

a plurality of metal pads, each being underlying and contacting one of the plurality of via portions, wherein each of the plurality of metal pads extends laterally beyond a corresponding edge of the pad portion.

12. The package of claim 11 further comprising a dielectric layer comprising:

a first portion encircling the plurality of via portions and the plurality of metal pads; and

second portions extending into the plurality of metal pads.

13. The package of claim 12 , wherein each of the second portions penetrates through a respective one of the plurality of metal pads.

14. The package of claim 12 , wherein the dielectric layer comprises a polymer.

15. The package of claim 12 , wherein the second portions of the dielectric layer are arranged as an array comprising a plurality of rows and a plurality of columns.

16. The package of claim 12 , wherein the two-terminal passive device die extends laterally beyond edges of the conductive feature.

17. A package comprising:

a dielectric layer;

a plurality of metal pads in the dielectric layer;

an Under-Bump Metallurgy (UBM) comprising a plurality of via portions in the dielectric layer, wherein each of the plurality of via portions is over and contacting one of the plurality of metal pads;

a solder region over and contacting the UBM, wherein each of the plurality of metal pads comprises a portion extending laterally beyond corresponding edges of the solder region and the UBM; and

a passive device comprising a terminal, wherein the terminal is over and joined to the solder region.

18. The package of claim 17 , wherein the UBM further comprises a pad portion over the dielectric layer, and wherein the solder region is joined to the pad portion.

19. The package of claim 17 , wherein the dielectric layer comprises portions extending into, and penetrating through, the plurality of metal pads.

20. The package of claim 17 , wherein the passive device comprises a capacitor.

Continuity (4)
Continuation 17188534 · Mar 1, 2021
Division 16203919 · Nov 29, 2018
Division 14979954 · Dec 28, 2015
Related Publication 20220361332A1 · Nov 10, 2022