Storage device and operating method thereof
A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.
1. A memory device, comprising:
a clock generator generating a data processing clock signal based on an external clock signal; and
an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal,
wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.
2. The memory device of claim 1 , wherein the clock generator further comprises a pause detector detecting the pause period based on the data processing clock signal.
3. The memory device of claim 2 , wherein the pause detector comprises:
a counter counting a number of toggles of the data processing clock signal according to a counter enable signal; and
a counter controller generating the counter enable signal when the data processing clock signal is detected.
4. The memory device of claim 3 ,
wherein the counter controller further generates a count check signal having a predetermined period, and
wherein the pause detector detects whether the pause period exists according to the predetermined period.
5. The memory device of claim 3 , wherein the counter controller further disables the counter enable signal when the pause period is detected.
6. The memory device of claim 3 , wherein the pause detector further includes a comparator comparing the number of toggles of the data processing clock signal with a predetermined number to detect the pause period.
7. The memory device of claim 6 , wherein the comparator further generates, when the pause period is detected, a warm-up reset signal for the warm-up operation controller to reset the warm-up enable signal in response to the warm-up reset signal.
8. The memory device of claim 1 , wherein the clock generator recognizes a portion of the period of the external clock signal, which is resumed as the dummy signal when an input of the external clock signal is resumed.
9. The memory device of claim 8 , wherein the warm-up operation controller generates the warm-up enable signal to recognize the portion of the period of the external clock signal, which is resumed, as the dummy signal.
10. The memory device of claim 1 , wherein the portion of the period corresponds to a predetermined time interval after the external clock signal is input to the clock generator.
11. A method of operating a memory device transmitting/receiving data to/from an external device, the method comprising:
receiving an external clock signal;
generating a warm-up enable signal to recognize a portion of a period of the external clock signal as a dummy signal;
generating a data processing clock signal based on the warm-up enable signal and the external clock signal;
detecting a pause period where a toggle of the external clock signal is temporarily stopped; and
resetting the warm-up enable signal when the pause period is detected.
12. The method of claim 11 , wherein the detecting of the pause period comprises detecting the pause period based on the data processing clock signal.
13. The method of claim 12 , wherein the detecting of the pause period comprises:
generating a count enable signal when the data processing clock signal is detected; and
counting a number of toggles of the data processing clock signal according to the count enable signal.
14. The method of claim 13 , wherein the detecting of the pause period further comprises detecting whether the pause period exists according to a predetermined period.
15. The method of claim 13 , wherein the detecting of the pause period further comprises disabling the count enable signal when the pause period is detected.
16. The method of claim 11 , wherein the pause period is detected by comparing a number of toggles of the data processing clock signal with a predetermined number.
17. The method of claim 11 , wherein the resetting of the warm-up enable signal comprises generating, when the pause period is detected, a warm-up reset signal to reset the warm-up enable signal.
18. The method of claim 11 , further comprising, when an input of the external clock signal, which is resumed after the pause period, generating the warm-up enable signal to recognize the portion of the period of the external clock signal as the dummy signal.
19. The method of claim 11 , wherein the portion of the period corresponds to a predetermined time interval after the external clock signal is input to the memory device.
20. A semiconductor apparatus comprising:
an operation control circuit configured to perform an operation according to a first clock signal; and
a clock generating circuit configured to:
enable, in response to activation of a second clock signal, a warm-up enable signal at a predetermined amount of time after the activation to activate the first clock signal, the second clock signal having a leading deactivated time section and the first clock signal having a lagging deactivated time section; and
disable the warm-up enable signal when detecting the lagging deactivated time section.