IP Library Granted Patent US 11,615,214
Granted Patent B2
US 11,615,214 · App. 16/913,748 · Granted Mar 28, 2023

Cryptographic key management

Inventors: Juane Li (Milpitas, CA); Jiangli Zhu (San Jose, CA); Ying Yu Tai (Mountain View, CA)
Assignee: Micron Technology, Inc.
G06F21/79G06F21/602G11C29/42G11C29/44H04L9/0866H04L9/0869H04L9/0891
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Quick Facts
Patent No.
US 11,615,214
App. No.
16/913,748
Granted
Mar 28, 2023
Kind
B2
Abstract

Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.

Claims (67)

1. A method, comprising:

receiving, by a hardware component, a command from a firmware component, the command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device;

generating, by the hardware component, the first cryptographic key based at least in part on the command;

generating, by the hardware component and based at least in part on generating the first cryptographic key, an initialization vector that is based at least in part on the user data, or the first cryptographic key, or a combination thereof;

encrypting, by the hardware component, the first cryptographic key using a second cryptographic key stored at a first register of a set of registers of the hardware component and the initialization vector; and

communicating the encrypted first cryptographic key to a nonvolatile memory device for storage, the nonvolatile memory device separate from the hardware component.

2. The method of claim 1 , further comprising:

generating, by the hardware component, error correction information for the encrypted first cryptographic key; and

communicating the error correction information to the nonvolatile memory device for storage based at least in part on communicating the encrypted first cryptographic key to the nonvolatile memory device for storage.

3. The method of claim 1 , further comprising:

storing the first cryptographic key in a first volatile memory device of the hardware component, wherein the first cryptographic key comprises an encryption key for encrypting the user data.

4. The method of claim 3 , further comprising:

storing a third cryptographic key in a second volatile memory device of the hardware component, wherein the third cryptographic key comprises a decryption key for decrypting the user data, and wherein the first volatile memory device is different than the second volatile memory device.

5. The method of claim 3 , further comprising:

receiving, by the hardware component, the encrypted first cryptographic key from the nonvolatile memory device; and

performing an error correction operation on the first cryptographic key stored in the first volatile memory device based at least in part on the receiving the encrypted first cryptographic key.

6. The method of claim 1 , further comprising:

receiving, from a host device, an access command associated with the user data stored on the memory device; and

encrypting or decrypting the user data using the first cryptographic key and the initialization vector based at least in part on the receiving the access command.

7. The method of claim 1 , further comprising:

receiving, by the hardware component, the encrypted first cryptographic key from the nonvolatile memory device; and

decrypting, by the hardware component, the encrypted first cryptographic key using the second cryptographic key and the initialization vector.

8. The method of claim 7 , further comprising:

receiving, by the hardware component, error correction information associated with the encrypted first cryptographic key from the nonvolatile memory device; and

performing, by the hardware component, an error correction operation on the encrypted first cryptographic key based at least in part on the receiving the error correction information, wherein decrypting the encrypted first cryptographic key is based at least in part on the performing the error correction operation.

9. The method of claim 1 , further comprising:

receiving, by the hardware component, a second command to generate an updated first cryptographic key for encrypting or decrypting the user data stored on the memory device;

generating, by the hardware component, the updated first cryptographic key based at least in part on the receiving the second command; and

encrypting, by the hardware component, the updated first cryptographic key using the second cryptographic key and the initialization vector.

10. The method of claim 9 , further comprising:

detecting, by the hardware component, that a quantity of errors within the encrypted first cryptographic key satisfies a threshold of errors, wherein the receiving the second command is based at least in part on detecting that the quantity of errors within the encrypted first cryptographic key satisfies the threshold of errors.

11. The method of claim 9 , wherein generating the updated first cryptographic key further comprises:

generating a first set of random data;

determining that the first set of random data and the first cryptographic key comprise a same set of data;

generating a second set of random data based at least in part on the determining that the first set of random data and the first cryptographic key comprise the same set of data; and

determining that the second set of random data and the first cryptographic key comprise a different set of data, wherein the updated first cryptographic key comprises the second set of random data based at least in part on the determining that the second set of random data and the first cryptographic key comprise the different set of data.

12. The method of claim 1 , further comprising:

generating, by the hardware component, a third cryptographic key associated with the first cryptographic key, wherein the third cryptographic key is different than the first cryptographic key, and wherein one of the first cryptographic key or the third cryptographic key is for encrypting the user data and the other of the first cryptographic key or the third cryptographic key is for decrypting the user data.

13. A system, comprising:

a random information generator of a hardware component configured to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device;

a volatile memory device of the hardware component configured to store the first cryptographic key;

an encryption engine of the hardware component configured to:

generate an initialization vector that is based at least in part on the user data, or the first cryptographic key, or a combination thereof, and

encrypt the first cryptographic key using a second cryptographic key stored at a first register of a set of registers of the hardware component and the initialization vector; and

a buffer of the hardware component configured to store the encrypted first cryptographic key during a communication of the encrypted first cryptographic key associated with the system and a firmware component.

14. The system of claim 13 , further comprising an error correction code (ECC) encoder configured to:

generate error correction information for performing an error correction operation on the encrypted first cryptographic key; and

store the encrypted first cryptographic key and the error correction information at the buffer.

15. The system of claim 13 , further comprising an error correction code (ECC) decoder configured to:

receive error correction information and the encrypted first cryptographic key from the buffer; and

perform an error correction operation on the encrypted first cryptographic key using the error correction information.

16. The system of claim 13 , further comprising a decryption engine configured to:

receive the encrypted first cryptographic key from the buffer; and

decrypt the encrypted first cryptographic key using the second cryptographic key and the initialization vector.

17. The system of claim 13 ,

wherein the set of registers receives the second cryptographic key from the firmware component.

18. A method, comprising:

receiving, by a hardware component from a nonvolatile memory device, an encrypted first cryptographic key and a second cryptographic key, wherein the encrypted first cryptographic key is for encrypting or decrypting user data stored on a memory device, and wherein the second cryptographic key is stored at a first register of a set of registers of the hardware component;

generating, by the hardware component, an initialization vector that is based at least in part on the user data, or the first cryptographic key, or a combination thereof;

decrypting, by the hardware component, the encrypted first cryptographic key using the second cryptographic key and the initialization vector; and

storing the first cryptographic key in a volatile memory device on the hardware component based at least in part on decrypting the encrypted first cryptographic key.

19. The method of claim 18 , further comprising:

receiving, by the hardware component from the nonvolatile memory device, error correction information associated with the encrypted first cryptographic key; and

performing, by the hardware component, an error correction operation on the encrypted first cryptographic key using the error correction information.

20. The method of claim 18 , further comprising:

receiving, from a host device, an access command associated with the user data stored on the memory device; and

encrypting or decrypting the user data using the first cryptographic key and the initialization vector based at least in part on the receiving the access command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2020
From: LI, JUANE; ZHU, JIANGLI; TAI, YING YU
To: MICRON TECHNOLOGY, INC
Reel/Frame 053315/0358 →
Continuity (2)
Provisional Application 62874437 · Jul 15, 2019
Related Publication 20210019450A1 · Jan 21, 2021