Variable resistance memory device

1. A variable resistance memory device comprising:

a plurality of memory cells arranged on a substrate, each of the memory cells comprising a selection element pattern and a variable resistance pattern stacked on the substrate,

wherein the selection element pattern comprises:

a first selection element pattern including a chalcogenide material; and

a second selection element pattern including a metal oxide and coupled to the first selection element pattern,

wherein the first selection element pattern has a first conductivity type and the second selection element pattern has a second conductivity type different from the first conductivity type.

2. The variable resistance memory device of claim 1 , wherein the second selection element pattern forms a pn junction with the first selection element pattern.

3. The variable resistance memory device of claim 1 , wherein the second selection element pattern has an energy band gap greater than an energy band gap of the first selection element pattern.

4. The variable resistance memory device of claim 3 , wherein the energy band gap of the first selection element pattern ranges from 1.1 eV to 2.25 eV, and the energy band gap of the second selection element pattern ranges from 2.3 eV to 4.0 eV.

5. The variable resistance memory device of claim 3 , wherein the chalcogenide material comprises at least one of tellurium (Te) and selenium (Se) and at least one of germanium (Ge), antimony (Sb), bismuth (Bi), lead (Pb), tin (Sn), silver (Ag), arsenic (As), sulfur (S), silicon (Si), Indium (In), titanium (Ti), gallium (Ga), phosphorus (P), oxygen (O), and carbon (C), and the metal oxide of the second selection element pattern comprises oxygen (O) and at least one of zinc (Zn), indium (In), gallium (Ga), and tin (Sn).

6. The variable resistance memory device of claim 1 , wherein each of the memory cells further comprises a first electrode, a second electrode, and a third electrode stacked on the substrate, the selection element pattern is disposed between the first and second electrodes, the variable resistance pattern is disposed between the second and third electrodes, the first selection element pattern is in contact with one of the first and second electrodes, and the second selection element pattern is in contact with the other of the first and second electrodes.

7. The variable resistance memory device of claim 6 , wherein the second selection element pattern is interposed between the first electrode and the first selection element pattern.

8. The variable resistance memory device of claim 1 , further comprising:

first conductive lines arranged in parallel with one another on the substrate and extending in a first direction; and

a second conductive line extending in a second direction crossing the first conductive lines,

wherein the memory cells are disposed at respective intersection regions of the first conductive lines and the second conductive line.

9. The variable resistance memory device of claim 1 , wherein a thickness of the second selection element pattern is 5% to 17% of a thickness of the first selection element pattern.

10. A semiconductor device, comprising:

a plurality of first conductive lines disposed on a substrate and spaced apart from each other;

a plurality of memory cells disposed on the first conductive lines, respectively, each of the memory cells comprising a selection element pattern and a variable resistance pattern stacked on the substrate; and

a second conductive line connected to the memory cells, the second conductive line crossing the first conductive lines,

wherein the selection element pattern comprises:

a first selection element pattern including a chalcogenide material; and

a second selection element pattern including a metal oxide in direct contact with the first selection element pattern,

wherein the second selection element pattern has a conductivity type different from that of the first selection element pattern.

11. The semiconductor device of claim 10 , wherein the second selection element pattern has an energy band gap greater than that of the first selection element pattern.

12. The semiconductor device of claim 10 , wherein each of the memory cells further comprises a first electrode, a second electrode, and a third electrode, the selection element pattern is disposed between the first and second electrodes, the variable resistance pattern is disposed between the second and third electrodes, the first selection element pattern is in contact with one of the first and second electrodes, and the second selection element pattern is in contact with the other of the first and second electrodes.

13. The semiconductor device of claim 10 , wherein each of the memory cells further comprises:

an insulating pattern having a trench; and

a lower barrier layer provided in a lower region of the trench, wherein the variable resistance pattern is disposed on a top surface of the lower barrier layer to fill a remaining empty region of the trench.

14. The semiconductor device of claim 10 , wherein a thickness of the first selection element pattern ranges from 80 Å to 300 Å, and a thickness of the second selection element pattern ranges from 4 Å to 50 Å.

15. A variable resistance memory device comprising:

a substrate;

a first conductive line disposed on the substrate and extending in a first direction;

a second conductive line disposed on the first conductive line and extending in a second direction crossing the first direction; and

a memory cell disposed between the first and second conductive lines and at an intersection of the first and second conductive lines,

wherein the memory cell comprises:

a selection element pattern;

a variable resistance pattern disposed on the selection element pattern;

a first electrode disposed between the selection element pattern and the first conductive line;

a second electrode between the selection element pattern and the variable resistance pattern; and

a third electrode disposed between the variable resistance pattern and the second conductive line, and

wherein the selection element pattern comprises:

a first selection element pattern including a chalcogenide material; and

a second selection element pattern including a metal oxide and coupled to the first selection element pattern,

wherein the second selection element pattern forms a pn junction with the first selection element pattern.

16. The variable resistance memory device of claim 15 , wherein the second selection element pattern has an energy band gap greater than that of the first selection element pattern.

17. The variable resistance memory device of claim 15 , wherein each of the memory cells further comprises a barrier pattern interposed between the second electrode and the variable resistance pattern, and the variable resistance pattern is spaced apart from the second electrode.

18. The variable resistance memory device of claim 15 , wherein each of the memory cells further comprises a barrier pattern interposed between the variable resistance pattern and the third electrode, and the variable resistance pattern is spaced apart from the third electrode.