Storage device and operating method thereof

1. A storage device comprising:

a nonvolatile memory comprising power loss protector (PLP) memory blocks configured to store at least one of meta data or user data for data backup;

a buffer memory configured to store at least one of the meta data or the user data stored in the PLP memory blocks;

a charging circuit configured to

generate electric power for data backup in response to a sudden power off (SPO) occurrence, and

generate a first charging complete signal or a second charging complete signal according to a level of the electric power; and

a processor configured to control at least one of the nonvolatile memory or the buffer memory to

restore the meta data from the PLP memory blocks to the buffer memory in response to the first charging complete signal, and

restore the user data from the PLP memory blocks to the buffer memory in response to the second charging complete signal.

2. The storage device of claim 1 , wherein the buffer memory comprises:

a first buffer memory configured to store the meta data; and

a second buffer memory configured to store the user data.

3. The storage device of claim 2 , wherein the charging circuit comprises a first region,

wherein the first region is configured to generate electric power for writing the meta data stored in the first buffer memory to a PLP memory block corresponding to a power cycle after SPO, and

the charging circuit is configured to transmit the first charging complete signal to the processor in response to capacitors included in the first region becoming completely charged.

4. The storage device of claim 3 , wherein the charging circuit further comprises a second region,

wherein the second region is configured to generate electric power for writing the user data stored in the second buffer memory in the PLP memory block corresponding to the power cycle after SPO, and

wherein the charging circuit is configured to transmit the second charging complete signal to the processor in response to capacitors included in the second region becoming completely charged.

5. The storage device of claim 2 , wherein the charging circuit is configured to:

transmit the first charging complete signal to the processor in response to the electric power generated by the charging circuit being at a first level or higher; and

transmit the second charging complete signal to the processor in response to the electric power generated by the charging circuit being at a second level or higher, the second level being higher than the first level.

6. The storage device of claim 2 , wherein the first buffer memory and the second buffer memory are configured to be allocated in one buffer memory.

7. The storage device of claim 2 , wherein the first buffer memory and the second buffer memory are configured to be allocated to a plurality of different buffer memories.

8. The storage device of claim 1 , wherein the processor comprises a plurality of cores, and

the nonvolatile memory comprises the PLP memory blocks for each core.

9. An operating method of a storage device, wherein the storage device comprises a nonvolatile memory comprising a first power loss protector (PLP) memory block corresponding to an Nth power cycle and a second PLP memory block corresponding to a (N+1)th power cycle, the operating method comprising:

when power is applied to the storage device, reading meta data from the first PLP memory block in response to a first charging complete signal;

storing the meta data in a first buffer memory of the storage device;

reading user data from the first PLP memory block in response to a second charging complete signal; and

storing the user data in a second buffer memory of the storage device,

wherein N is an integer greater than or equal to 0.

10. The operating method of claim 9 , wherein the storage device further comprises a charging circuit configured to generate electric power for data backup, and

the operating method further comprises:

generating the first charging complete signal in response to electric power generated by the charging circuit being at a first level or higher; and

generating the second charging complete signal in response to the electric power generated by the charging circuit being at a second level or higher, the second level being higher than the first level.

11. The operating method of claim 9 , further comprising:

receiving, from a host, a read command for the meta data stored in the first buffer memory; and

providing the meta data to the host in response to the read command.

12. The operating method of claim 9 , further comprising:

writing the meta data stored in the first buffer memory and the user data stored in the second buffer memory to the second PLP memory block in response to a sudden power off (SPO) occurrence.

13. The operating method of claim 9 , further comprising:

receiving a write command for new meta data from a host; and

storing the new meta data in the first buffer memory in response to the write command.

14. The operating method of claim 13 , further comprising:

writing the new meta data stored in the first buffer memory and the user data stored in the second buffer memory to the second PLP memory block in response to a sudden power off (SPO) occurrence.

15. The operating method of claim 9 , further comprising:

receiving a write command for new user data from a host;

storing the new user data in the second buffer memory in response to the write command; and

writing the meta data stored in the first buffer memory and the new user data stored in the second buffer memory to the second PLP memory block in response to a sudden power off (SPO) occurrence.

16. An operating method of a storage device, wherein the storage device comprises a nonvolatile memory comprising a first power loss protector (PLP) memory block corresponding to an Nth power cycle and a second PLP memory block corresponding to a (N+1)th power cycle,

the operating method comprising:

storing meta data stored in the first PLP memory block in a first buffer memory of the storage device in response to power being applied to the storage device;

storing user data stored in the first PLP memory block in a second buffer memory of the storage device in response to power being applied to the storage device; and

writing the meta data and the user data to the second PLP memory block in response to a sudden power off (SPO) occurrence,

wherein N is an integer greater than or equal to 0.

17. The operating method of claim 16 , further comprising:

receiving a write command for new meta data from a host before the SPO occurrence;

storing the new meta data in the first buffer memory in response to the write command before the SPO occurrence; and

writing the new meta data and the user data to the second PLP memory block in response to the SPO occurrence.

18. The operating method of claim 16 , further comprising:

receiving a write command for new user data from a host before the SPO occurrence;

storing the new user data in the second buffer memory in response to the write command before the SPO occurrence; and

writing the meta data and the new user data to the second PLP memory block in response to the SPO occurrence.

19. The operating method of claim 16 , wherein the first buffer memory and the second buffer memory of the storage device are configured to be allocated to a plurality of different buffer memories.

20. The operating method of claim 16 , wherein the storage device comprises a multi-core processor comprising a plurality of cores, and

the nonvolatile memory comprises the first PLP memory block and the second PLP memory block for each core.