Cache replacement policy for ray tracing

1. A processor configured to implement a cache replacement policy, comprising:

circuitry configured to issue a memory request for attribute information associated with a node in an acceleration data structure; and

circuitry configured to, responsive to the memory request causing a cache miss, insert the attribute information associated with the node into a cache entry of the cache, and set an age associated with the cache entry to a value based on the attribute information;

wherein the attribute information associated with the node indicates a level of the node within the acceleration data structure.

2. The processor of claim 1 , wherein the attribute information comprises metadata associated with the acceleration data structure and the age is set based on the metadata.

3. The processor of claim 1 , wherein the attribute information comprises information associated with a level of the node within the acceleration data structure and the age is set based on the information associated with the level of the node.

4. The processor of claim 1 , wherein the attribute information comprises information associated with a parent of the node within the acceleration data structure and the age is set based on the information associated with the information associated with the parent.

5. The processor of claim 1 , further comprising circuitry configured to, responsive to the memory request hitting the cache, set the age associated with the cache entry to a value based on the attribute information.

6. The processor of claim 1 , further comprising circuitry configured to, responsive to the memory request hitting the cache, set the age associated with the cache entry to a value associated with a cache hit.

7. The processor of claim 1 , further comprising circuitry configured to, responsive to the memory request missing the cache, evict information from the cache entry prior to inserting the attribute information associated with the node into the cache entry.

8. The processor of claim 1 , further comprising circuitry configured to, responsive to the memory request missing the cache, determine the cache entry from among a plurality of entries of the cache based on the age associated with the cache entry.

9. A method for implementing a cache replacement policy, the method comprising:

issuing a memory request for attribute information associated with a node in an acceleration data structure; and

responsive to the memory request causing a cache miss, inserting the attribute information associated with the node into a cache entry of the cache, and setting an age associated with the cache entry to a value based on the attribute informations;

wherein the attribute information associated with the node indicates a level of the node within the acceleration data structure.

10. The method of claim 9 , wherein the attribute information comprises metadata associated with the acceleration data structure and the age is set based on the metadata.

11. The method of claim 9 , wherein the attribute information comprises information associated with a level of the node within the acceleration data structure and the age is set based on the information associated with the level of the node.

12. The method of claim 9 , wherein the attribute information comprises information associated with a parent of the node within the acceleration data structure and the age is set based on the information associated with the information associated with the parent.

13. The method of claim 9 , further comprising, responsive to the memory request hitting the cache, setting the age associated with the cache entry to a value based on the attribute information.

14. The method of claim 9 , further comprising, responsive to the memory request hitting the cache, setting the age associated with the cache entry to a value associated with a cache hit.

15. The method of claim 9 , further comprising, responsive to the memory request missing the cache, evicting information from the cache entry prior to inserting the attribute information associated with the node into the cache entry.

16. The method of claim 9 , further comprising, responsive to the memory request missing the cache, determining the cache entry from among a plurality of entries of the cache based on the age associated with the cache entry.

17. A processor configured to perform ray tracing, comprising:

circuitry configured to cast a ray through a three-dimensional (3D) model space;

circuitry configured to determine an intersection between the ray and a primitive within the 3D model space, wherein the primitive is associated with a node in an acceleration data structure;

circuitry configured to issue a memory request for attribute information associated with the primitive; and

circuitry configured to, responsive to the memory request causing a cache miss, insert the attribute information associated with the primitive into a cache entry of the cache, and to set an age associated with the cache entry to a value based on the attribute information;

wherein the attribute information associated with the node indicates a level of the node within the acceleration data structure.

18. The processor of claim 17 , wherein the attribute information comprises metadata associated with the acceleration data structure and the age is set based on the metadata.

19. The processor of claim 17 , wherein the attribute information comprises information associated with a level of the node within the acceleration data structure and the age is set based on the information associated with the level of the node.

20. The processor of claim 17 , wherein the attribute information comprises information associated with a parent of the node within the acceleration data structure and the age is set based on the information associated with the information associated with the parent.