IP Library › Granted Patent US 11,625,247
Granted Patent B2
US 11,625,247 · App. 17/471,387 · Granted Apr 11, 2023

System for executing new instructions and method for executing new instructions

Inventors: Weilin Wang (Beijing, CN); Yingbing Guan (Beijing, CN); Mengchen Yang (Beijing, CN)
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
G06F9/30145G06F9/30101G06F9/30189G06F9/4812
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Quick Facts
Patent No.
US 11,625,247
App. No.
17/471,387
Granted
Apr 11, 2023
Kind
B2
Abstract

A method for executing new instructions includes receiving an instruction, and determining whether the received instruction is a new instruction according to an operation code of the received instruction. When the received instruction is a new instruction, the basic decoding information of the received instruction is stored in a private register. And, the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information includes the operation code.

Claims (48)

1. A method for executing new instructions, comprising:

receiving an instruction; and

determining whether the received instruction is a new instruction according to an operation code of the received instruction; and

when the received instruction is a new instruction:

storing basic decoding information of the received instruction into a private register, wherein the basic decoding information comprises the operation code; and

entering a system management mode, and simulating the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode.

2. The method for executing new instructions of claim 1 , wherein when the received instruction is a new instruction, the method for executing new instructions further comprises:

decoding the received instruction to obtain the basic decoding information of the received instruction; and

reading the basic decoding information from the private register, and storing the read basic decoding information in the system management memory.

3. The method for executing new instructions of claim 1 , wherein when the received instruction is a new instruction, the method for executing new instructions further comprises:

setting an emulation flag in a private register to a first value; and

entering the system management mode according to the emulation flag in the private register.

4. The method for executing new instructions of claim 1 , wherein when the received instruction is a new instruction, the method for executing new instructions further comprises:

if the received instruction needs to access the memory, then the received instruction is decoded into a special microinstruction, wherein the special microinstruction comprises an emulation flag;

when the emulation flag of the special microinstruction is a first value, using the special microinstruction to check permissions of the received instruction, and generating a check result; and

storing the check result in the private register.

5. The method for executing new instructions of claim 1 , wherein when the received instruction is the new instruction and an operand of the received instruction is a new architecture register, in the system management mode, the new architecture register is simulated by a special register or a system management memory.

6. The method for executing new instructions of claim 5 , wherein when the new architecture register is a destination operand of the received instruction, the method for executing new instructions further comprises:

after simulation execution of the received instruction is completed, storing the simulation execution result of the received instruction in the special register or the system management memory.

7. The method for executing new instructions of claim 6 , wherein when the new architecture register is a destination operand of the received instruction, the method for executing new instructions further comprises:

when exiting the system management mode, doing not store the simulation execution result stored in the special register or the system management memory into an architecture register.

8. The method for executing new instructions of claim 6 , further comprising:

receiving another instruction; and

when the another instruction is a new instruction, and the new architecture register is the source operand of the another instruction, directly using the simulation execution result stored in the special register or the system management memory to simulate the execution of the another instruction.

9. The method for executing new instructions of claim 1 , further comprising:

decoding the received instruction into a microinstruction, wherein the microinstruction comprises an emulation flag;

generating a system management interrupt according to the emulation flag of the microinstruction; and

entering the system management mode according to the system management interrupt.

10. The method for executing new instructions of claim 9 , wherein when the received instruction is a new instruction, the method for executing new instructions further comprises:

When retiring the microinstruction, generating the system management interrupt according to the emulation flag of the microinstruction.

11. A system for executing new instructions, comprising:

an instruction monitoring unit, configured to receive an instruction, and to determine whether the received instruction is a new instruction according to an operation code of the received instruction;

an instruction decoding unit, when the received instruction is a new instruction, the instruction decoding unit stores basic decoding information of the received instruction in a private register; and

the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information comprises the operation code.

12. The system for executing new instructions of claim 11 , wherein when the received instruction is a new instruction, the instruction decoding unit decodes the received instruction to obtain the basic decoding information of the received instruction;

the system for executing the new instructions reads the basic decoding information from the private register, and stores the read basic decoding information into the system management memory.

13. The system for executing new instructions of claim 11 , when the received instruction is a new instruction, and the system for executing new instructions further comprises:

a private register, wherein the system for executing instructions sets the emulation flag in the private register to a first value, and enters the system management mode according to the emulation flag in the private register.

14. The system for executing new instructions of claim 11 , further comprising:

a memory access unit, wherein when the received instruction is a new instruction, if the received instruction needs to access the memory, the system for executing the new instruction decodes the received instruction into a special microinstruction; wherein the special microinstruction includes an emulation flag, and when the emulation flag of the special microinstruction is a first value, the memory access unit uses the special microinstruction to check permissions of the received instruction to generate a check result, and stores the check result in the private register.

15. The system for executing new instructions of claim 11 , further comprising:

a special register, wherein when the received instruction is a new instruction, and an operand of the received instruction is a new architecture register, in the system management mode, the new architecture register is simulated using the special register or a system management memory.

16. The system for executing new instructions of claim 15 , wherein when the new architecture register is a destination operand of the received instruction, after the system for executing the new instruction simulates the execution of the received instruction, the system for executing the new instructions stores the simulation execution result of the received instruction in the special register or the system management memory.

17. The system for executing new instructions of claim 16 , wherein when the new architecture register is the destination operand of the received instruction, when exiting the system management mode, the system for executing the new instructions does not store the simulation execution result stored in the special register or the system management memory into an architecture register.

18. The system for executing new instructions of claim 16 , wherein the instruction monitoring unit receives another instruction; when the another instruction is a new instruction, and the new architecture register is the source operand of the another instruction, the system for executing the new instructions directly uses the simulation execution result stored in the special register or in the system management memory to simulate the execution of the another instruction.

19. The system for executing new instructions of claim 11 , wherein the instruction decoding unit decodes the received instruction into a microinstruction; wherein the microinstruction comprises an emulation flag; the system for executing the new instruction generates a system management interrupt according to the emulation flag of the microinstruction, and enters the system management mode according to the system management interrupt.

20. The system for executing new instructions of claim 19 , further comprising:

an instruction retiring unit, when the microinstruction is retired, the system management interrupt is generated according to the emulation flag of the microinstruction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2021
From: WANG, WEILIN; GUAN, YINGBING; YANG, MENGCHEN
To: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Reel/Frame 057442/0639 →
Priority Claims (2)
CN 202011591545.6 · Dec 29, 2020 · national
CN 202011591894.8 · Dec 29, 2020 · national
Continuity (1)
Related Publication 20220206810A1 · Jun 30, 2022