IP Library Granted Patent US 11,625,335
Granted Patent B2
US 11,625,335 · App. 17/170,460 · Granted Apr 11, 2023

Adaptive address translation caches

Inventors: Sagar Borikar (San Jose, CA); Ravikiran Kaidala Lakshman (San Jose, CA)
Assignee: Cisco Technology, Inc.
G06F12/1081G06F12/12G06F13/122G06F2213/0026
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Quick Facts
Patent No.
US 11,625,335
App. No.
17/170,460
Granted
Apr 11, 2023
Kind
B2
Abstract

Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.

Claims (52)

1. A method comprising:

in response to an untranslated address not existing in a first level of cache of an address translation cache (ATC), determining whether the untranslated address is associated with one or more pinned entries in a second level of cache of the ATC;

in response to the untranslated address not being associated with the one or more pinned entries in the second level of cache of the ATC, determining one or more reserved regions of the first level of cache associated with the one or more pinned entries;

updating the first level of cache of the ATC to invalidate any entries not included in the one or more reserved regions;

transmitting a translation request to retrieve a translated address associated with the untranslated address;

in response to the translation request being validated to access memory storing the translated address, receiving the translated address; and

updating, at the first level of cache of the ATC, a mapping of the translated address with the untranslated address.

2. The method of claim 1 , wherein the translation request is an aggregate of a plurality of translation requests.

3. The method of claim 1 , further comprising:

in response to a change in a translation of the translation address, receiving an invalidation request; and

clearing a subset of an address range in the ATC.

4. The method of claim 1 , wherein the translation request is a read or write request from the memory.

5. The method of claim 1 , further comprising:

in response to determining that the ATC requires access to a page which is unavailable, transmitting a page request; and

receiving the page from memory.

6. The method of claim 5 , wherein the page request included at least a page address or a page request group index.

7. The method of claim 5 , wherein the page is received via a root complex.

8. At least one non-transitory computer readable medium, storing instructions, which when executed cause at least one processor to:

in response to an untranslated address not existing in a first level of cache of an address translation cache (ATC), determine whether the untranslated address is associated with one or more pinned entries in a second level of cache of the ATC;

in response to the untranslated address not being associated with the one or more pinned entries in the second level of cache of the ATC, determine one or more reserved regions of the first level of cache associated with the one or more pinned entries;

update the first level of cache of the ATC to invalidate any entries not included in the one or more reserved regions;

transmit a translation request to retrieve a translated address associated with the untranslated address;

in response to the translation request being validated to access memory storing the translated address, receive the translated address; and

update, at the first level of cache of the ATC, a mapping of the translated address with the untranslated address.

9. The at least one non-transitory computer readable medium of claim 8 , wherein the translation request is an aggregate of a plurality of translation requests.

10. The at least one non-transitory computer readable medium of claim 8 , further comprising:

in response to a change in a translation of the translation address, receiving an invalidation request; and

clearing subset of an address range in the ATC.

11. The at least one non-transitory computer readable medium of claim 8 , wherein the translation request is a read or write request from the memory.

12. The at least one non-transitory computer readable medium of claim 8 , further comprising:

in response to determining that the ATC requires access to a page which is unavailable, transmitting a page request; and

receiving the page from memory.

13. The at least one non-transitory computer readable medium of claim 12 , wherein the page request included at least a page address or a page request group index.

14. The at least one non-transitory computer readable medium of claim 12 , wherein the page is received via a root complex.

15. A system comprising:

an endpoint comprising an address translation cache (ATC);

a root complex; and

a memory,

the system configured to:

in response to an untranslated address not existing in a first level of cache of an address translation cache (ATC), determine whether the untranslated address is associated with one or more pinned entries in a second level of cache of the ATC;

in response to the untranslated address not being associated with the one or more pinned entries in the second level of cache of the ATC, determine one or more reserved regions of the first level of cache associated with the one or more pinned entries;

update the first level of cache of the ATC to invalidate any entries not included in the one or more reserved region;

transmit, from the ATC to the memory via the root complex, a translation request to retrieve a translated address associated with the untranslated address;

in response to the translation request being validated to access the memory storing the translated address, receive, from the memory via the root complex to the endpoint, the translated address; and

update, at the first level of cache of the ATC, a mapping of the translated address with the untranslated address.

16. The system of claim 15 , wherein the system is further configured to:

in response to a change in a translation of the translation address, receive an invalidation request; and

clear subset of an address range in the ATC.

17. The system of claim 15 , wherein the system is further configured to:

in response to determining that the ATC requires access to a page which is unavailable, transmitting a page request; and

receiving the page from memory.

18. The system of claim 17 , wherein the page request included at least a page address or a page request group index.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2021
From: BORIKAR, SAGAR; LAKSHMAN, RAVIKIRAN KAIDALA
To: CISCO TECHNOLOGY, INC.
Reel/Frame 055185/0542 →
Continuity (2)
Continuation 16290101 · Mar 1, 2019
Related Publication 20210182212A1 · Jun 17, 2021
Cited By (8)
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