A/D converter including comparison circuit and image sensor including same

1. An image sensor comprising:

a pixel array comprising a plurality of pixels;

a ramp signal generator configured to generate a ramp signal; and

a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal,

wherein the comparison circuit comprises:

a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node;

a limiter comprising an n-type transistor having one end connected to the first circuit node and an opposite end to which a power supply voltage is applied; and

a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal,

wherein the limiter is configured to prevent reduction of the first stage output signal below a particular voltage independent of the comparison result signal.

2. The image sensor of claim 1 , wherein the power supply voltage is applied directly from a power supply terminal to a gate of the n-type transistor.

3. The image sensor of claim 1 , further comprising a timing generator configured to control operations of the ramp signal generator and the comparison circuit,

wherein the n-type transistor provides current to the first circuit node in response to a current control signal provided by the timing generator.

4. The image sensor of claim 1 , wherein the limiter further comprises a buffer connected to a gate of the n-type transistor.

5. The image sensor of claim 4 , further comprising a timing generator controlling operations of the ramp signal generator and the comparison circuit,

wherein the buffer provides a power supply voltage to the gate of the n-type transistor in response to a current control signal having high level provided by the timing generator.

6. The image sensor of claim 1 , wherein the limiter further comprises an inverter connected to a gate of the n-type transistor.

7. The image sensor of claim 6 , further comprising a timing generator controlling operations of the ramp signal generator and the comparison circuit,

wherein the inverter provides a power supply voltage to the gate of the n-type transistor in response to a current control signal having low level provided by the timing generator.

8. The image sensor of claim 1 , wherein the first comparator stage outputs a second signal to a second circuit node, and

the first comparator stage further comprises a p-type transistor connected between the first circuit node and the second circuit node.

9. The image sensor of claim 1 , wherein the first comparator stage outputs a second output signal to a second circuit node, and

the first comparator stage further comprises an n-type transistor connected between the first circuit node and the second circuit node.

10. The image sensor of claim 1 , wherein the ramp signal generator generates the ramp signal, and the ramp signal gradually increases during an operation period in which the comparison circuit compares the pixel signal to the ramp signal.

11. The image sensor of claim 10 , wherein the pixel signal comprises a reset signal output by a pixel of the plurality of pixels during a reset operation, and an image signal output before the reset signal, wherein the pixel signal is generated by the pixel by performing a photo-sensing operation, and

the comparison circuit compares the reset signal with the ramp signal, after comparing the image signal with the ramp signal.

12. The image sensor of claim 10 , wherein the pixel signal comprises a reset signal output by a pixel of the plurality of pixels during a reset operation, and an image signal output after the reset signal, wherein the pixel signal is generated by the plurality of pixels by performing a photo-sensing operation, and

the comparison circuit compares the image signal with the ramp signal, after comparing the reset signal with the ramp signal.

13. An analog-to-digital (A/D) converter configured to convert a pixel signal output by a pixel array to a digital signal, the A/D converter comprising:

a first comparator stage configured to output, to a first circuit node, a first stage output signal according to a result of comparing the pixel signal with a ramp signal;

a limiter configured to limit a voltage level of the first stage output signal by providing current to the first circuit node; and

a second comparator stage configured to generate a comparison result signal by shaping the first stage output signal,

wherein the limiter comprises an n-type transistor having one end connected to the first circuit node and an opposite end to which a power supply voltage is applied, the limiter being configured to prevent reduction of the first stage output signal below a particular voltage independent of the comparison result signal.

14. The A/D converter of claim 13 , wherein the power supply voltage is also applied directly from a power supply terminal to a gate of the n-type transistor.

15. The A/D converter of claim 13 , wherein the limiter further comprises a buffer connected to a gate of the n-type transistor.

16. The A/D converter of claim 13 , wherein the limiter further comprises an inverter connected to a gate of the n-type transistor.

17. The A/D converter of claim 13 , wherein the first comparator stage outputs a second signal to a second circuit node, and

the first comparator stage comprises a p-type transistor connected between the first circuit node and the second circuit node, and a gate thereof is connected to the first circuit node.

18. The A/D converter of claim 13 , wherein the first comparator stage outputs a second signal to a second circuit node, and

the first comparator stage comprises an n-type transistor connected between the first circuit node and the second circuit node, and a gate thereof connected to the second circuit node.

19. The A/D converter of claim 13 , wherein the ramp signal has a positive slope during a certain period.

20. The A/D converter of claim 15 , further comprising:

a counter configured to generate the digital signal by determining a count at a logic level transition time of the comparison result signal using a counting clock signal.