Frequency and gain calibration for time synchronization in a network

1. A transceiver comprising:

a transmit chain;

a receive chain;

a first clock; and

a processor configured to:

transmit a first calibration signal at a first time-of-departure measured by the first clock; and

transmit a second calibration signal at a second time-of-departure measured by the first clock and succeeding transmission of the first calibration signal by an initial signal interval;

receive a first time-of-arrival of the first calibration signal at a second transceiver, the first time-of-arrival measured by a second clock of the second transceiver;

receive a second time-of-arrival of the second calibration signal at the second transceiver measured by the second clock of the second transceiver;

define a first calibration point, in a first set of calibration points, the first calibration point representing the first time-of-departure and the first time-of-arrival;

define a second calibration point, in the first set of calibration points, the second calibration point representing the second time-of-departure and the second time-of-arrival; and

calculate a first frequency offset between the first clock and the second clock based on the first set of calibration points.

2. The transceiver of claim 1 , wherein the processor is further configured to calculate the first frequency offset between the first clock and the second clock by:

calculating a first regression on the first set of calibration points; and

calculating a slope of the first regression and solving for c 1 −c 2 in: β=1+c 1 −c 2 , wherein β represents a slope of the first regression, wherein c 1 represents a first frequency offset of the first clock from a nominal frequency, and wherein c 2 represents a second frequency offset of the second clock from the nominal frequency.

3. The transceiver of claim 2 , wherein the processor is further configured to:

calculate a residual of the first regression;

calculate an adjusted signal interval based on the residual of the first regression;

transmit a third calibration signal at a third time-of-departure measured by the first clock;

transmit a fourth calibration signal at a fourth time-of-departure measured by the first clock and succeeding transmission of the third calibration signal by the adjusted signal interval;

receive a third time-of-arrival of the third calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

receive a fourth time-of-arrival of the fourth calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

define a third calibration point in a second set of calibration points, the third calibration point representing the third time-of-departure and the third time-of-arrival;

define a fourth calibration point in the second set of calibration points, the fourth calibration point representing the fourth time-of-departure and the fourth time-of-arrival; and

calculate a second frequency offset between the first clock and the second clock based on the second set of calibration points.

4. The transceiver of claim 3 , wherein the processor is further configured to calculate the adjusted signal interval based on residual of the first regression by calculating the adjusted signal interval based on a desired accuracy and the residual of the first regression.

5. The transceiver of claim 4 , wherein the processor is further configured to calculate the adjusted signal interval based on a desired accuracy and the residual of the first regression by:

calculating an outlier probability based on a timestamping noise;

calculating a number of calibration signals for an adjusted calibration period based on the desired accuracy and the outlier probability; and

dividing the adjusted calibration period by the number of calibration signals to calculate the adjusted signal interval.

6. The transceiver of claim 2 , wherein the processor is further configured to:

transmit a third calibration signal at a third time-of-departure measured by the first clock and succeeding transmission of the first calibration signal by an initial calibration period;

receive a third time-of-arrival of the third calibration signal at the second transceiver measured by the second clock of the second transceiver; and

define a final calibration point of the first set of calibration points, the final calibration point of the first set of calibration points comprising the third time-of-departure and the third time-of-arrival.

7. The transceiver of claim 6 , wherein the processor is further configured to:

calculate a timestamping noise of the second clock relative to the first clock based on a residual of the first regression;

calculate an adjusted calibration period based on a desired precision and the timestamping noise;

transmit a fourth calibration signal at a fourth time-of-departure measured by the first clock;

transmit a fifth calibration signal at a fifth time-of-departure measured by the first clock and succeeding transmission of the fourth calibration signal by an adjusted single interval;

transmit a sixth calibration signal at a sixth time-of-departure measured by the first clock and succeeding transmission of the fourth calibration signal by the adjusted calibration period;

receive a fourth time-of-arrival of the fourth calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

receive a fifth time-of-arrival of the fifth calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

receive a sixth time-of-arrival of the sixth calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

define a fourth calibration point in a second set of calibration points, the fourth calibration point representing the fourth time-of-departure and the fourth time-of-arrival;

define a fifth calibration point in the second set of calibration points, the fifth calibration point representing the fifth time-of-departure and the fifth time-of-arrival;

define a sixth calibration point in the second set of calibration points, the sixth calibration point of the second set of calibration points comprising the sixth time-of-departure and the sixth time-of-arrival; and

calculate a second frequency offset between the first clock and the second clock based on the second set of calibration points.

8. The transceiver of claim 7 , wherein the processor is further configured to calculate the adjusted calibration period by solving for m max −m min in: m max −m min >Δ max /δ, wherein Δ max represents the timestamping noise, wherein δ represents the desired precision, and wherein m max −m min represents the adjusted calibration period.

9. The transceiver of claim 1 , wherein the processor is further configured to:

access a first set of clock characteristics of the first clock;

access a second set of clock characteristics of the second clock; and

calculate the initial signal interval based on the first set of clock characteristics and the second set of clock characteristics.

10. The transceiver of claim 1 , wherein the processor is further configured to, in response to detecting a change in temperature at the transceiver:

transmit a third calibration signal at a third time-of-departure measured by the first clock;

transmit a fourth calibration signal at a fourth time-of-departure measured by the first clock;

receive a third time-of-arrival of the third calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

receive a fourth time-of-arrival of the fourth calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

define a third calibration point in a second set of calibration points, the third calibration point representing the third time-of-departure and the third time-of-arrival;

define a fourth calibration point in the second set of calibration points, the fourth calibration point representing the fourth time-of-departure and the fourth time-of-arrival; and

calculate a second frequency offset between the first clock and the second clock based on the second set of calibration points.

11. The transceiver of claim 1 , wherein the processor is further configured to, in response to detecting motion at the transceiver:

transmit a third calibration signal at a third time-of-departure measured by the first clock;

transmit a fourth calibration signal at a fourth time-of-departure measured by the first clock;

receive a third time-of-arrival of the third calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

receive a fourth time-of-arrival of the fourth calibration signal at the second transceiver measured by the second clock of the second transceiver adjusted by the first frequency offset;

define a third calibration point in a second set of calibration points, the third calibration point representing the third time-of-departure and the third time-of-arrival;

define a fourth calibration point in the second set of calibration points, the fourth calibration point representing the fourth time-of-departure and the fourth time-of-arrival; and

calculate a second frequency offset between the first clock and the second clock based on the second set of calibration points.

12. The transceiver of claim 1 , wherein the processor is further configured to:

transmit the first calibration signal at the first time-of-departure measured by the first clock of the first transceiver by transmitting the first calibration signal at a first phase-of-departure measured by the first clock of the first transceiver, the first phase-of-departure, ∠ 1,1 , equal to 2πf c T 1,1 mod 2π, wherein:

T 1,1 represents the first time-of-departure; and

f c represents a carrier frequency of the first calibration signal;

transmit the second calibration signal at the second time-of-departure measured by the first clock and succeeding the first time-of-departure by an initial signal interval comprises transmitting the second calibration signal at a second phase-of-departure measured by the first clock, the second phase-of-departure, ∠ 2,1 , equal to 2πf c T 2,1 mod 2π, wherein T 2,1 represents the second time-of-departure;

receive the first time-of-arrival of the first calibration signal at the second transceiver, the first time-of-arrival measured by the second clock of the second transceiver by receiving a first phase-of-arrival of the first calibration signal at the second transceiver measured by the second clock of the second transceiver, the first phase-of-arrival, ∠ 1,2 , equal to 2πf c T 1,2 mod 2π, wherein T 1,2 represents the first phase-of-arrival; and

receive the second time-of-arrival of the second calibration signal at the second transceiver, the second time-of-arrival measured by the second clock of the second transceiver by receiving a second phase-of-arrival of the second calibration signal at the second transceiver measured by the second clock of the second transceiver, the second phase-of-arrival, ∠ 2,2 , equal to 2πf c T 2,2 mod 2π, wherein T 2,2 represents the second phase-of-arrival.

13. The transceiver of claim 12 , wherein the processor is further configured to:

for each carrier frequency, f c , in a range of carrier frequencies, calculating ∠ 1,1 , ∠ 2,1 , ∠ 1,2 , and ∠ 2,2 ;

define the first calibration point, in the first set of calibration points, the first calibration point representing the first phase-of-departure and the first phase-of-arrival by, for each carrier frequency, f c , in the range of carrier frequencies, defining the first calibration point, in the first set of calibration points as (∠ 1,1 , ∠ 1,2 );

define a second calibration point, in the first set of calibration points, the second calibration point representing the second phase-of-departure and the second phase-of-arrival by, for each carrier frequency, f c , in the range of carrier frequencies, defining the second calibration point, in the first set of calibration points as (∠ 2,1 , ∠ 2,2 ); and

calculate the first frequency offset between the first clock and the second clock based on the first set of calibration points by calculating the first frequency offset between the first clock and the second clock based on the first set of calibration points for each carrier frequency, f c , in the range of carrier frequencies.

14. The transceiver of claim 1 , wherein the first clock comprises a crystal oscillator clock.

15. The transceiver of claim 1 , wherein the processor is further configured to compensate the first clock by the first frequency offset.

16. A server comprising a processor configured to:

schedule transmission, from a first transceiver, of a first calibration signal at a first time-of-departure measured by a first clock of the first transceiver;

schedule transmission, from the first transceiver, of a second calibration signal at a second time-of-departure measured by the first clock and succeeding transmission of the first calibration signal by an initial signal interval;

receive, from a second transceiver, a first time-of-arrival measured by a second clock of the second transceiver, the first time-of-arrival corresponding to reception of the first calibration signal at the second transceiver;

receive, from the second transceiver, a second time-of-arrival measured by the second clock, the second time-of-arrival corresponding to reception of the second calibration signal at the second transceiver;

define a first calibration point in a first set of calibration points, the first calibration point representing the first time-of-departure and the first time-of-arrival;

define a second calibration point in the first set of calibration points, the second calibration point representing the second time-of-departure and the second time-of-arrival; and

calculating a first frequency offset between the first clock and the second clock based on the first set of calibration points.

17. The server of claim 16 , wherein the processor is further configured to schedule a data transfer slot for the first transceiver, the data transfer slot characterized by a slot duration less than the initial signal interval by at least a duration of the first calibration signal.

18. The server of claim 16 , wherein the processor is further configured to:

schedule transmission, from the first transceiver, of the first calibration signal at the first time-of-departure by scheduling transmission, from the first transceiver, of the first calibration signal at the first time-of-departure during a transmission slot at the first transceiver;

schedule transmission, from the first transceiver, of the second calibration signal at the second time-of-departure by scheduling transmission, from the first transceiver, of the second calibration signal at the second time-of-departure during the transmission slot at the first transceiver; and

schedule, at the second transceiver, a reception slot spanning the transmission slot at the first transceiver.

19. The server of claim 16 , wherein the processor is further configured to:

receive, from a third transceiver, a third time-of-arrival measured by a third clock of the third transceiver, the third time-of-arrival corresponding to reception of the first calibration signal at the third transceiver;

receive, from the third transceiver, a fourth time-of-arrival measured by the third clock, the fourth time-of-arrival corresponding to reception of the second calibration signal at the third transceiver;

define a third calibration point in a second set of calibration points, the third calibration point representing the first time-of-departure and the third time-of-arrival;

define a fourth calibration point in the second set of calibration points, the fourth calibration point representing the second time-of-departure and the fourth time-of-arrival; and

calculate a second frequency offset between the first clock and the third clock based on the second set of calibration points.

20. The server of claim 16 , wherein the processor is further configured to:

calculating a first regression based on the first set of calibration points;

calculate a timestamping noise of the second clock relative to the first clock based on a residual of the first regression;

calculate an adjusted signal interval based on the timestamping noise;

schedule transmission, from the first transceiver, of a third calibration signal at a third time-of-departure measured by the first clock;

schedule transmission, from the first transceiver, of a fourth calibration signal at a fourth time-of-departure measured by the first clock and succeeding transmission of the third calibration signal by the adjusted signal interval;

receive, from a third transceiver, a third time-of-arrival measured by a third clock of the third transceiver, the third time-of-arrival corresponding to reception of the third calibration signal at the third transceiver;

receive, from the third transceiver, a fourth time-of-arrival measured by the third clock, the fourth time-of-arrival corresponding to reception of the fourth calibration signal at the third transceiver;

define a third calibration point in a second set of calibration points, the third calibration point representing the third time-of-departure and the third time-of-arrival;

define a fourth calibration point in the second set of calibration points, the fourth calibration point representing the fourth time-of-departure and the fourth time-of-arrival; and

calculate a second frequency offset between the first clock and the third clock based on the second set of calibration points.